CX82100 Home Network Processor Data Sheet
to be stored at the same cluster location. The limiter, DMA_{X}_Cnt1, is used to prevent
the EMAC-RxD channel from overwriting the allocated cluster buffer size.
The protocol for this DMA channel is:
1. ARM initializes the CDT.
2. ARM initializes DMA_{X}_Ptr2 with the base pointer to CDT (a copy saved within
DMAC).
3. ARM initializes DMA_{X}_Cnt1 to limit number of qwords written to cluster.
4. ARM initializes DMA_{X}_Cnt2 for CDT circular size in qwords.
5. DMAC prefetches first cluster pointer from DMA_{X}_Ptr2+ = 8 (post-increments
by 8).
6. DMAC moves prefetched cluster pointer into DMA_{X}_Ptr1 and prefetches second
cluster pointer from DMA_{X}_Ptr2+8 (no post-increment).
7. EMAC-RxD issues DMA_SAVE, DMAC saves cluster head ptr.
8. EMAC-RxD issues DMA_XNUL, DMA_{X}_Ptr1+ = 8, DMA_{X}_Cnt1++.
9. EMAC-RxD issues DMA_XNXT, DMAC saves data to DMA_{X}_Ptr1+ = 8,
DMA_{X}_Cnt1++.
10. Continue with step 8 until entire packet data is received.
11. EMAC-RxD issues DMA_XSAV, DMAC saves status to DMA_{X}_Ptr2+ = 16.
12. EMAC-RxD issues DMA_XNXT, DMAC saves 0 to DMA_{X}_Ptr1+ = 8,
DMA_{X}_Cnt1++.
13. EMAC-RxD issues DMA_INTR, DMAC sets DMA interrupt for RxD channel.
14. DMAC moves prefetched cluster pointer into DMA_{X}_Ptr1 and prefetches next
cluster pointer from DMA_{X}_Ptr2+8 (no post-increment).
The ARM may read DMA_{X}_Ptr2 at anytime to know where the DMAC is currently
processing the table (recall that the DMAC is prefetching cluster pointers). The ARM can
also determine that a EMAC-RxD status qword location has been updated by looking at
bit 3 which is always written with a 1’b1, if it initializes the status qwords with zero and
as it consumes clusters (and ptrs).
Since the CDT operates in circular mode, all ptr2 prefetches and post-increments operate
modulo 8*DMA_Cnt2.
4.6.3
Linked List Mode
There are two linked list modes supported in the current design: 1) embedded tail linked
list descriptor mode and 2) indirect/table linked list descriptor mode. The first mode is
supported for all transmit channels except channel 7 (memory-to-memory DMAs). The
second mode is supported only for USB transmit channels, i.e., channels 9, 10, 11, and
13. The linked list mode can be programmed through the "DMAC_{x}_LMode" field in
the DMAC_{x}_Cnt1 registers.
Embedded Tail Linked List Descriptor Mode
For the Embedded Tail Linked List Descriptor mode, the buffer link descriptor (ptr/cnt) is
embedded in the buffer at its tail end. Figure 4-2 shows an example for this linked list
mode. This tail linked list is a generic example of how the transmitted packets are set up.
The Ctl_Hdr is specific to the type of DMA being performed, e.g., EMAC, and should be
configured accordingly.
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