CX82100 Home Network Processor Data Sheet
The usage of each register for controlling the operation of the circular buffer is as
follows:
•
DMAC_{x}_Ptr2. Used as a base pointer to a dword-aligned circular buffer and is
loaded by the microcontroller (by writing to DMAC_{x}_Ptr1) just once (i.e., this
pointer value is fixed) after the buffer has been allocated. This buffer is typically big
enough to handle multiple data packets (packet size is 64 bytes for USB). The buffer
must be a whole multiple of qwords.
•
DMAC_{x}_Ptr1. Used as the current pointer, pointing to the next qword to be
transferred. This pointer is constructed by adding 8*(DMAC_{x}_Cnt2 –
DMAC_{x}_Cnt1) to the base pointer DMA{x}_Ptr2. The constructed
DMAC_{x}_Ptr1 is the value read when reading its register location (writing has no
effect for the Circular Buffer mode).
•
•
DMAC_{x}_Cnt1. Loaded with an 11-bit value representing the size of the entire
circular buffer. The same value is copied to DMAC_{x}_Cnt2 during write to
DMAC_{x}_Cnt1. This counter register is decremented by one as a qword transfer
is processed. When DMA{x}_Cnt1 = 0, it is reloaded with DMAC_{x}_Cnt2.
DMAC_{x}_Cnt2. Loaded with an 11-bit value representing the size of the entire
circular buffer. This value is not changed during the course of data transfers.
Indirect Circular Pointer Table
The indirect circular pointer table is explained with an example of how the EMAC RxD
channels work. The EMAC-RxD channel (channel 2 or 4) requires its data to be stored in
memory buffers where the location of each buffer is chosen by the firmware on a pointer
per packet basis. Each received data packet is stored in a contiguous memory segment of
fixed size. This size must be large enough to handle the largest expected packet (plus
overhead), usually less than 1536 bytes (192 qwords). The data is normally going to
remain stationary until transmitted or consumed. The circular data buffer method is not
appropriate for this channel because it would require the data to be consumed in the order
received otherwise the data would have to be copied to other buffers which consumes a
lot of bus bandwidth.
The DMA_{x}_Ptr2, where {x} = 2 or 4, is used to point to the location of the table
which contains the list of pointers to be used for the received data destination buffers.
This table holds the following 4-dword structures called cluster descriptors:
Table 4-4. Cluster Descriptor Table
Cluster Descriptor Table (CDT) ⇐ DMA_{x}_Ptr2, where {x} = 2 or 4
CD No.
qword
dword
1
1
2
Cluster Pointer 1
Reserved
EMAC-RxD Status [31:0] for packet 1
EMAC-RxD Status [63:32] for packet 1
Cluster Pointer N
N
2N-1
2N
Reserved
EMAC-RxD Status [31:0] for packet N
EMAC-RxD Status [63:32] for packet N
The cluster descriptors include status that is written back from the EMAC for each
received packet. When DMA_{x}_Ptr2 is written, a copy is saved as the base pointer to
the head of the pointer table (CDT). The DMA_{x}_Ptr2 can be read anytime to indicate
where the DMAC is currently at in the CDT. The CDT is a circular buffer. The size in
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