CX82100 Home Network Processor Data Sheet
Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)
Pin Signal
Pin No.
I/O
I/O Type
Signal Name/Description
LAN 1 Receive Data. For MII interface, EM1_RXD[3:0] are the 4-
bit parallel receive data lines. Connect EM1_RXD[3:0] to LAN 1
PHY RXD[3:0] through 51 Ω.
For 7-WS interface, EM1_RXD3 is the Receive input bit stream.
Connect EM1_RXD3 to LAN 1 EPHY RXD pin through 51 Ω.
EM1_RXD[2:0] are not used and should be left open.
LAN 1 Receive Data Valid. EM1_RXDV is asserted by the LAN 1
EPHY to indicate that the nibble on EM1_RXD[3:0] is valid. It
remains asserted for the received frame duration with the exception
of the preamble. It may or may not be asserted during the
preamble. EM1_RXDV is de-asserted prior to the first
EM1_RX_CLK period that follows the final nibble of a received
frame. When EM1_RXDV is de-asserted, the EMAC ignores
EM1_RXD[3:0].
EM1_RXD[3:0]
H2, H1, H3, H4
I
I
Itpd
EM1_RXDV
EM1_RXER
L7
Itpd
Itpd
For MII, connect to LAN 1 EPHY RX_DV pin through 51 Ω.
For 7-WS interface, leave open (not used).
LAN 1 Receive Error. EM1_RXER is driven by the LAN 1 EPHY. It
is asserted for one or more EM1_RX_CLK periods to indicate that
an error was detected somewhere in the frame presently being
transferred from the LAN 1 EPHY. The RMAC hardware will detect
this condition and declare such a frame invalid. While EM1_RXDV
is deasserted, EM1_RXER has no effect on the Reconciliation
sublayer (which lies between the MII and the MAC), therefore, it
has no effect on the MAC as well.
For MII, connect to LAN 1 EPHY RX_RXER pin through 51 Ω.
For 7-WS interface, leave open (not used).
Transmit Clock. EM1_TX_CLK is sourced by the LAN 1 EPHY. It
provides the timing reference for the transfer of EM1_TX_EN,
EM1_TXD[3:0], and EM1_TXER signals to LAN 1 EPHY.
P8
I
I
EM1_TX_CLK
EM1_TX_EN
E1
F1
Itpd
For MII, connect to LAN 1 EPHY TX_CLK pin through 51 Ω.
For 7-WS interface, connect to LAN PHY TX_CLK pin through
51 Ω.
LAN 1 Transmit Enable. EM1_TX_EN is driven off the rising edge
and sampled on the rising edge of EM1_TX_CLK. It indicates that
the HNP is presenting nibbles on the MII for transmission.
O
O
Otts4
EM1_TX_EN is asserted when the HNP has data to transmit over
the medium and remains asserted for the duration of the entire
transmitted frame. The HNP de-asserts EM1_TX_EN prior to the
rising edge of EM1_TX_CLK following the final nibble of a frame.
For MII, connect to LAN 1 EPHY TX_EN pin.
For 7-WS interface, connect to LAN 1 EPHY TX_EN pin.
LAN 1 Transmit Data. For MII interface, EM1_TXD[3:0] are the 4-
bit parallel transmit data lines. EM1_TXD[3:0] is driven off the rising
edge and sampled on the rising edge of EM1_TX_CLK. The entire
transmitted frame data is presented by the EM1_TXD[3:0] signal
lines, and commences on the first leading edge of EM1_TX_CLK
subsequent to EM1_TX_EN assertion. For each EM1_TX_CLK
period in which EM1_TX_EN is asserted, EM1_TXD[3:0] are
accepted for transmission by the LAN 1 EPHY. All fields except for
the FCS are transmitted with the least significant nibble first. The
LSb of each nibble is placed on EM1_TXD0. Connect
EM1_TXD[3:0]
E4, F3, F5, F2
Otts4
EM1_TXD[3:0] to LAN 1 EPHY TXD[3:0] through 51 Ω.
For 7-WS interface, EM1_TXD3 is the transmit input bit stream.
Connect EM1_TXD3 to LAN 1 EPHY TXD pin. EM1_TXD[2:0] are
not used and should be left open.
101306C
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CONEXANT [ CONEXANT SYSTEMS, INC ]
