CX82100 Home Network Processor Data Sheet
Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)
Pin Signal
Pin No.
I/O
I/O Type
USB Interface
Signal Name/Description
USBP
USBN
D9
E8
I/O
Iu/Ou
USB Port. USBP and USBN are the differential data positive and
negative signals of the USB port. Connect USBP and USBN to
USB +Data and -Data, respectively, through 24 Ω, and optionally
through a quick switch in order to isolate the USBP and USBN from
the USB during suspend mode.
USB_PWR_DET C9
(GPIO22)
I
It/Ot4
Itpu
USB Power Detect. Active high input used to detect presence of
+5 V at the USB connector.
JTAG Interface
JTAG Reset. A high-to-low transition on this signal forces the TAP
TRST#
TCK
TMS
TDI
J4
K2
J6
K1
K3
I
controller into a logic reset state. This pin has an internal pullup.
Leave open for normal operation.
I
Itpu
JTAG Test Clock. This is the boundary scan clock input signal.
This pin has an internal pullup.
Leave open for normal operation.
I
Itpu
JTAG Test Mode Select. This signal controls the operation of the
TAP controller. This pin has an internal pull-up.
Leave open for normal operation.
I
Itpu
JTAG Test Input. This signal contains serial data that is shifted in
on the rising edge of TCK. The pin has an internal pullup.
Leave open for normal operation.
TDO
O
Otts4
JTAG Test Output Data. This is the three-stateable boundary scan
data output signal from the MCU, and it is shifted out on the falling
edge of TCK.
Leave open for normal operation.
Test Interface Controller (TIC) [Factory Test Only]
Itpd
Reserved. This pin is connected to internal circuitry. Leave open.
TREQA
K5
I
101306C
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