CX82100 Home Network Processor Data Sheet
Table 2-3. CX82100 HNP Pin Signal Definitions
Pin Signal
Pin No.
I/O
I/O Type
Power and Ground
Signal Name/Description
VDD
VDDA
VDDO
H7, H8
G6
A12, B3, B5,
D1, D14, F6,
F9, F12, H10,
J7, K7, K11,
N5, N9, N11,
P1
P
P
P
PWR
PWR
PWR
Core Supply Voltage. Connect to +1.8V.
Supply Voltage. Connect to +1.8V through filter.
I/O Supply Voltage. Connect to +3.3V.
VDDO
VGG
N13 (CX82100
P
R
PWR
REF
I/O Supply Voltage. Connect to +3.3V.
-11/-12/-51/-52)
I/O Clamp Power Supply. Connect to +5V if available, otherwise
H6
connect to +3.3V.
VSS
VSSA
VSSO
G7, G8
H5
A5, B9, B11,
C4, D8, D12,
F4, G9, H11,
K13, L2, N8,
P2, P5, P9,
P11
G
G
G
GND
GND
GND
Core Ground. Connect to digital ground.
Ground. Connect to digital ground.
I/O Ground. Connect to digital ground.
VSSO
VSSO
N13 (CX82100
G
G
GND
GND
I/O Ground. Connect to digital ground.
I/O Ground. Connect to digital ground.
–41/-42)
P13 (CX82100
-11/-12/-51/-52)
System Control
HRST#
N14
I
Ith
Reset. Active low input asserted for at least 100 µs to reset the
HNP. All hardware registers are initialized to their default state.
Upon de-assertion of HRST#, the HNP executes the Boot Loader
code (see BOPT pin) then starts processing of the application
code.
Connect HRST# to a reset circuit.
BOPT (GPIO14)
PLLBP
K4
J3
I/O
I
Itpu/Ot4
Itpd
Boot Loader Option. Upon de-assertion of the HRST# signal, the
Boot Loader code executes from internal ROM (BOPT pin high, i.e.,
open) or Flash ROM (BOPT pin low, i.e., connected to GND).
For normal operation, typically connect BOPT to GND through
4.7 kΩ to execute Boot Loader from Flash ROM.
PLL Bypass Mode Select. If the PLLBP pin is high (test mode),
pins FCLKIO and BCLKIO are FCLKIO and BCLKIO inputs only
(i.e., not GPIO pins). If the PLLBP pin is low (normal operation),
pins FCLKIO and BCLKIO operate as FCLKIO/GPIO39 and
BCLKIO/GPIO38 as selected in the GPIO_OPT register).
For normal operation, connect PLLBP to GND through 4.7 kΩ.
Clock Interface
Clock In. Connect to 35.328 MHz voltage controlled crystal
CLKI
J2
I
Ith
oscillator (VCXO) output through 51 Ω.
BCLKIO/GPIO38 J5
I/O
Itpu/Ot4
Bit Clock I/O. If PLLBP pin is high (test mode), this pin is BCLKIO
input only (i.e., not GPIO38). If the PLLBP pin is low (normal
operation), this pin can be used as GPIO38 or BCLKIO (see
GPIO_OPT register bit 6 and PLLBP pin).
For normal operation, BCLKIO output supplies the 25 MHz to the
LAN1 and LAN2 interfaces. Connect BCLKIO to the LAN 1 X1 pin
and to the LAN2 X1 pin though a single 51 Ω resistor.
Frame Clock I/O. If the PLLBP pin is high (test mode), this pin is
FCLKIO input only (i.e., not GPIO39). If the PLLBP pin is low
(normal operation), this pin can be used as GPIO39 or FCLKIO
(see GPIO_OPT register bit 7 and PLLBP pin).
FCLKIO/GPIO39 J1
I/O
Itpu/Ot4
2-8
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