CX82100 Home Network Processor Data Sheet
Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)
Pin Signal
Pin No.
I/O
I/O Type
EMAC 1 Interface
Signal Name/Description
EM1_COL
G1
I
I
Itpd
LAN 1 Collision Indication. In full-duplex mode, EM1_COL is
ignored. In half-duplex mode, EM1_COL is asserted by the LAN 1
EPHY upon detection of a collision on the medium, and remains
asserted while the collision condition persists.
For MII, connect to LAN 1 EPHY COL pin through 51 Ω.
For 7-WS interface, connect to LAN 1 EPHY COL pin through
51 Ω.
EM1_CRS
EM1_MDC
G2
Itpd
LAN 1 Carrier Sense. In full-duplex mode, EM1_CRS is ignored.
In half-duplex mode, EM1_CRS is asserted by the LAN 1 EPHY
when either the transmit or receive medium is not idle. It is de-
asserted by the LAN 1 EPHY when both the transmit and receive
media are idle. The LAN 1 EPHY ensures that EM1_CRS remains
asserted throughout the duration of a collision condition, i.e., when
EM1_COL = 1.
For MII, connect to LAN 1 EPHY CRS pin through 51 Ω.
For 7-WS interface, connect to LAN 1 EPHY CRS pin through
51 Ω.
K8
O
Otts4
LAN 1 Management Data Clock. EM1_MDC is sourced by the
Station Management entity (STA) of the EMAC as the timing
reference for transfer of information on the EM1_MDIO signal.
EM1_MDC is aperiodic and has no maximum high or low times.
The minimum high and low time for EM1_MDC is 160 ns each. The
minimum period for EM1_MDC is 400 ns.
For MII, connect to LAN 1 EPHY COL pin.
For 7-WS interface, leave open (not used).
EM1_MDIO
M8
G5
I/O
Itpd/Ot4
Itpd
LAN 1 Serial Management Data Input/Output. EM1_MDIO is a
bidirectional signal used to transfer control and status information
between the LAN 1 EPHY and the STA in the EMAC.
For MII, connect to LAN 1 EPHY MDIO pin and to +3.3V through
4.7 KΩ.
For 7-WS interface, connect to LAN 1 EPHY MDIO pin and to
+3.3V through 4.7 KΩ.
EM1_RX_CLK
I
LAN 1 Receive Clock. A 10 MHz square wave synchronized to the
Receive Data and only active while receiving an input bit stream.
EM1_RX_CLK is sourced by the LAN 1 EPHY. It provides the
timing reference for the transfer of EM1_RXDV, EM1_RXD[3:0],
and EM1_RXER signals from LAN 1 EPHY. The LAN 1 EPHY can
either recover EM1_RX_CLK from the received data or it may
derive EM1_RX_CLK from a nominal clock (e. g., the
EM1_TX_CLK reference). If loss of received signal from the
medium causes the LAN 1 EPHY to lose the recovered clock
reference, the LAN 1 EPHY must source the clock from a nominal
clock reference. Transitions from nominal clock to recovered clock
or vice versa are made only when EM1_RXDV is de-asserted.
During the interval between the assertion of EM1_CRS and the
assertion of EM1_RXDV at the beginning of a frame, the LAN 1
EPHY may extend a cycle of EM1_RX_CLK by holding it either
high or low until the LAN 1 EPHY has locked to the recovered
clock. Following the de-assertion of EM1_RXDV at the end of a
frame, the LAN 1 EPHY may extend a cycle of EM1_RX_CLK by
holding it either high or low for an interval not to exceed twice the
nominal clock period.
For MII, connect to LAN 1 EPHY RX_CLK pin 51 Ω.
For 7-WS interface, connect to LAN 1 EPHY RX_CLK pin 51 Ω.
2-10
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
