CX82100 Home Network Processor Data Sheet
8.5
8.6
Interrupt Endpoint
The interrupt endpoint is different from the other endpoints in that it does not get its data
from the TX DMA buffers or there is no TX DMA channel available for interrupt
endpoint. The interrupt endpoint relies on firmware writes to the U_IDAT register for the
interrupt data. Two writes to U_IDAT are required to furnish the 8 bytes of data for each
interrupt packet. After the first 4 bytes have been processed, a status bit
INTRNEXT_INT in U_STAT is set to indicate that the firmware can now write the next
4 bytes to U_IDAT. An INTRDN_INT status is set upon completion of the data transfer
to the host.
Summary of the Endpoints
The UDC Endpoints are summarized in Table 8-8.
Table 8-8. UDC Endpoints
UDC Logical Endpoint No.
Endpoint 0
Endpoint 0
Endpoint 1
Endpoint 1
Endpoint 2
Endpoint 2
Endpoint 3
Endpoint 3
UDC Physical Endpoint No.
Direction
IN
OUT
IN
OUT
IN
OUT
IN
Transfer Type
Control
Control
Bulk
Bulk
Bulk
Bulk
Bulk
Bulk
Interrupt
1
2
3
4
5
6
7
8
9
OUT
IN
Endpoint 4
8-14
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