CX82100 Home Network Processor Data Sheet
Table 8-4. Status qword for Receive (OUT) Endpoint APB Buffers
Bit(s)
63:16
15
14:12
11:8
7
Default
Name
Description
0
0
0
0
0
0
Reserved.
PKT_IN
Packet has been received without errors.
Reserved.
Endpoint address pointer that received this packet.
Current packet is a setup packet.
Count of data bytes received in this packet.
EP_NUM
SETUP
COUNT
6:0
After the DMA Channel 12 pointer and counter (circular RX DMA Buffer) and
EP_OUT_RX_BUFSIZE register are initialized, the RV_INIT bit in U_CTR1 register is
set and cleared (in the next instruction) before enabling endpoint OUT operation. This bit
is not set again until new RX DMA buffer setting is required and only when all receive
endpoints have been disabled. Data transfer from the host to the HNP commences if there
is space in the RX DMA buffer, and continues until the RX DMA buffer is full.
Requests to DMAC are generated whenever there is data in the RX FIFO of a given
endpoint, and USB ACK has not been received. Upon reception of USB ACK, data is
flushed into the RX DMA buffer, a qword Status Header is written to the beginning of
the buffer, and the EP_OUT_RX_PEND register is increased by one. Simultaneously, a
status bit (EP0O_INT, EP1O_INT, EP2O_INT, or EP3O_INT) is set in the U_STAT
register confirming the successful reception of data on that endpoint. A RX DMA
interrupt request is forwarded to the interrupt controller if the interrupt is enabled and
also if trigger conditions are satisfied. Interrupt events can be set from a variety of
interrupt sources: Single Packet Completion, Multiple Packet Completion, and/or Packet
Pending receive watchdog timeout.
The firmware parses the endpoint information from the Status Header and acts
accordingly. When any number of RX packets are safely processed by firmware, then the
same number is written to the EP_OUT_RX_DEC register so the UDC Core can reuse
the packets’ DMA buffers. There will be no new packets transferred to the RX DMA
buffer if EP_OUT_RX_PEND = EP_OUT_RX_BUFSIZE which also triggers an RX
DMA Overrun condition.
The USB RX DMA logic always initializes the next DMA Status Header packet with 0
after the first RX packet is received from the host. This can cause a problem if RX DMA
overrun condition happens (RX DMA buffer full with all 64 bytes packet size) due to
firmware overhead and system latency. Thus, it may be necessary to increase the
hardware buffer size by 8 bytes so that the most recent unprocessed Status Header
content is still intact if when overrun does occur. Note that DMAC Channel 12 count
register should be limited to 16376 bytes due to restriction of DMAC count register.
Since the maximum hardware RX DMA buffer for each data packet is 72 bytes (64 bytes
of data and 8 bytes of Status Header). With a given DMA RX buffer size in bytes, the
value programmed into the following registers should be:
DMAC_12_Cnt1 = (DMA RX buffer size) / 8
EP_OUT_RX_BUFSIZE = ((DMA RX buffer size) / 72) - 1
101306C
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