CX82100 Home Network Processor Data Sheet
8.3.3
Loading of the EndPtBuf Configurations
The endpoint configuration in the UDC Core is accomplished by writing to the U_CFG
register the same byte-wise data that the UDC Core expects. The target of these
configuration writes are the endpoint buffers which have the format shown in Table 8-1.
Starting from the Endpoint 0 descriptor (EndPtBuf0), the configuration data is written to
EndPtBuf0[39:32], followed by EndPtBuf0[31:24], and so on (EndPtBuf0 is reserved for
Endpoint 0). Once the 5-byte EndPtBuf0 has been filled, EndPtBuf1, and the others are
filled in order, most significant byte first. Since the register writes from APB are 4 bytes
in length, the data is grouped so that the first byte to the UDC interface comes from the
least significant byte of the register U_CFG. After the contents of the register write have
been passed on to the UDC Core, the firmware is requested, via the CFGNEXT_INT flag
in the U_STAT register, to write the next 4 bytes of configuration data. This continues
until the endpoint descriptors have been updated, with the assertion of CFGDN_INT
status. During configuration, the CFG_EN control bit is set to prevent any data from
being transferred to erroneous addresses. Once the configuration data has been loaded,
the CFG_EN bit is reset and endpoints are enabled through the setting of their enable bits
in the U_CTR1 register. Prior to enabling the endpoints, the endpoint addresses in the
U_CTR2 register must be programmed to match those passed to the endpoint descriptors
EP_BUFADRPTR parameters in the EndPtBuf.
USB GLOBAL EN bit (bit0 of U_CTR1) can only set once per POR or Hardware Reset
event, after that the UDC Core will accept the endpoint configuration data as described in
the sequences above. USB RESET bit (Bit 30 of U_CTR1) can be used to reset the UDC
Core the same way as POR or a Hardware Reset event.
Figure 8-5 shows the example of loading the EndPtBuf configurations described in Table
8-2.
8-8
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