CX82100 Home Network Processor Data Sheet
8.3
UDC Core
The USB Core includes the endpoint buffers and associated processing.
8.3.1
Endpoint Buffer Format
The UDC stores all the endpoint configuration information for each endpoint that the
HNP supports. Each endpoint configuration is stored in a separate Buffer called
EndPtBuf. The UDC Core has defined the logical and physical endpoints for its
implementation. A “logical endpoint” is an endpoint that is visible to the host. Generally,
for USB, there are 16 logical endpoints from the host’s perspective (Endpoint 0 to
Endpoint 15). At any time the host can access one of these logical endpoints. A “physical
endpoint”, on the other hand, is the actual unidirectional endpoint that is implemented in
the hardware. Two physical endpoints can be paired to form a bidirectional endpoint
sharing the same logical endpoint number.
The UDC supports one configuration, one interface, no alternate interface, three
bidirectional endpoints plus one interrupt endpoint (seven physical endpoints total). Since
each endpoint requires 5 bytes for its endpoint configuration, then the total number of
endpoint configuration bytes allocated within the UDC Core are (5 * 7) + 5 (Endpoint 0).
Firmware initializes these EndPtBuf Configuration bytes upon POR or Hardware Reset
event. Please refer to Section 8.3.3 for the procedure to initialize these Endpoint Buffer
Configurations.
Table 8-1. Endpoint Buffer Format in UDC Core
Bit(s)
39:36
35:34
Type
Description
EP_NUM
Logical Endpoint Number.
EP_CONFIG
Configuration Number.
Only configuration 1 is supported.
Interface Number.
Three interfaces (0, 1, or 2) are supported.
Alternate Setting.
Only alternate setting 0 for each interface is
33:32
31:29
EP_INTERFACE
EP_ALTSETTING
supported.
28:27
EP_TYPE
Type of Endpoint.
00 = Control.
01 = Isochronous.
10 = Bulk.
11 = Interrupt.
26
EP_DIR
Direction of Data Flow.
0 = Out.
1 = In.
This bit is ignored for control endpoints.
Maximum Packet Size for this Endpoint.
Address Pointer for the Associated Endpoint.
Only bits [3:0] are used.
25:16
15:0
EP_MAXPKTSIZE
EP_BUFADRPTR
This must match with the pointer specified in
U_CTR2 register for transfer to take place. It is
always zero for Endpoint 0.
8-6
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