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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Circuit Description  
CX28394/28395/28398  
2.3 System Bus  
Quad/x16/OctalT1/E1/J1 Framers  
64-Bit Elastic  
In 64-bit Elastic mode, the slip buffer total depth is 64 bits and the initial  
throughput delay is 32 bits, or one-half of the total depth. Similar to Normal  
mode, Elastic mode allows the system bus to operate at any of the programmable  
bus rates, independent of the line rate. The advantage of this mode over the  
two-frame mode is that throughput delay is reduced from one frame to an average  
of 32 bits, and the transmit multiframe can retain its alignment with respect to the  
transmit data. The disadvantage of this mode is handling the full and empty buffer  
conditions. In 64-bit Elastic mode, an empty or full buffer condition causes an  
Uncontrolled Slip (USLIP). Unlike an FSLIP, a USLIP is of unknown size,  
ranging from 1 to 256 bits of data. The USLIP status is reported in SSTAT.  
Two-Frame Short  
The Two-Frame Short mode combines the depth of the Normal mode with the  
throughput delay of the Elastic mode. This mode begins in Elastic mode with a  
32-bit initial throughput delay, and switches to Normal modes when the buffer is  
empty or full; thereafter, the Two-Frame Short and Normal modes perform  
identically. If the slip buffer is full (two frames) in the Two-Frame Short and  
normal modes, an FSLIP is reported; thereafter, the slip buffer performs exactly  
like Normal mode.  
Bypass  
In Bypass mode, data is clocked through TSLIP from the TSB to the XMTR  
using TXCLK as selected by the TXCLK input clock mux.  
2.3.5.3 Signaling Buffer  
The 32-byte Transmit Signaling Buffer [TSIG; addr 120–13F] stores a single  
multiframe of signaling data input from TSIGI pin and is updated as each time  
slot is received in every TSB frame. Each byte offset into TSIG is a different time  
slots signaling data: offset 0 stores TS0 signaling data, offset 1 stores TS1  
signaling data, etc. The signaling data is stored in the least significant 4 bits of the  
signaling buffer. Similar to TSLIP, TSIG has read/write processor access for  
accessing or overwriting signaling information. TFSYNC is used by the signaling  
buffer to identify the frame boundaries in the TSIGI data stream.  
2.3.5.4 Transmit  
Framing  
A transmit framing option is provided to allow the transmitter to automatically  
align to the transmit PCM data on TPCMI. In this mode, the Transmit Framer  
searches transmit data for a valid E1 or T1 framing pattern. The transmit data  
stream has two framing functions: offline framer and an online framer. The offline  
framer recovers the transmit frame alignment (TFSYNC). The online framer  
monitors the frame alignment found by the offline framer and recovers  
multiframe alignment (TMSYNC).  
Transmit Frame Alignment  
Transmit frame resynchronization is initiated by activating the Transmit Loss  
Of Frame (TLOF) status bit in the Alarm 2 status [ALM2; addr 048] register by  
the online framer. The TLOF criteria is set in the TLOFA, TLOFB, and TLOFC  
bits of the Transmitter Configuration register [TCR1; addr 071]. The online  
framer supports the following LOF criteria for T1: 2 frame bit errors out of 4, 2  
out of 5, or 2 out of 6; for E1, it supports 3 out of 3. Figure 2-19 illustrates  
transmit framing and timebase alignment options.  
2-36  
Conexant  
100054E  
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