2.0 Circuit Description
CX28394/28395/28398
2.3 System Bus
Quad/x16/Octal—T1/E1/J1 Framers
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B, C,
and D) of which one bus member is selected by the SBI [3:0] bits in the System
Bus Interface Configuration register [SBI_CR; 0D0] (see Figures 2-17 and 2-18).
The system bus rate is independent of the line rate and must be selected using the
System Bus Interface Configuration register.
Figure 2-17. TSB 4096K Bus Mode Time Slot Interleaving
TSBCKI
TPCMI
TS31A
TS31B
TS0A
TS0B
TSIGI
SIG31A
SIG31B
SIG0A
SIG0B
TFSYNC
NOTE(S): A and B time slot data comes from different framers. TSBCKI can be operated at 1 or 2 times the data rate.
Figure 2-18. TSB 8192K Bus Mode Time Slot Interleaving
TSBCKI
TPCMI
TSIGI
TS31A
TS31B
TS31C
TS31D
TS0A
TS0B
TS0C
TS0D
SIG31A
SIG31B
SIG31C
SIG31D
SIG0A
SIG0B
SIG0C
SIG0D
TFSYNC
NOTE(S): A, B, C, and D time slot data comes from different framers. TSBCKI can be operated at 1 or 2 times the data rate.
2-34
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
