3
3.17 Register Summary
Table 3-25. Global Control and Status Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
000
080
081
082
083
DID
FCR
MIR
MIE
TEST
R
DID[7]
GRESET
MIR[7]
MIE[7]
—
DID[6]
—
DID[5]
—
DID[4]
—
DID[3]
—
DID[2]
ONESEC_IO
MIR[2]
MIE[2]
DID[1]
SBIMODE[1]
MIR[1]
DID[0]
SBIMODE[0]
MIR[0]
MIE[0]
R/W
R
MIR[6]
MIE[6]
—
MIR[5]
MIE[5]
—
MIR[4]
MIE[4]
—
MIR[3]
MIE[3]
—
R/W
R/W
MIE[1]
—
TEST
—
Table 3-26. Primary Control Register
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
001
CR0
R/W
RESET
—
—
RFRAME[3]
RFRAME[2]
RFRAME[1]
RFRAME[0]
TI/EIN
Table 3-27. Interrupt Control Register
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
003
IRR
R
ALARM1
ALARM2
ERROR
COUNT
TIMER
DL1
DL2
PATT
CONEXANT [ CONEXANT SYSTEMS, INC ]
