Table 3-30. Primary Control and Status Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
014
015
016
017
018
019
01A
020
021
LOOP
DL3_TS
DL3_BIT
FSTAT
PIO
R/W
R/W
R/W
R
—
—
ODD
—
EVEN
—
PLOOP
TS[3]
LLOOP
TS[2]
FLOOP
TS[1]
—
TS[0]
DL3EN
TS[4]
DL3_BIT[7]
DL3_BIT[6]
—
DL3_BIT[5]
—
DL3_BIT[4]
INVALID
TDL_IO
RDL_OE
TSBCK
RAL_CON
EXZ
DL3_BIT[3]
FOUND
RFSYNC_IO
INDY_OE
—
DL3_BIT[2]
TIMEOUT
RMSYNC_IO
TCKO_OE
—
DL3_BIT[1]
ACTIVE
TFSYNC_IO
—
DL3_BIT[0]
RX/TXN
TMSYNC_IO
—
—
R/W
R/W
R/W
R/W
R
RMSYNC_EN
RDL_IO
—
TMSYNC_EN
TDL_OE
—
POE
—
—
—
—
CMUX
RAC
RSBCK
—
TXCLKI[1]
—
TXCLKI[0]
—
—
—
—
RSTAT
—
ZCSUB
BPV
—
—
—
Table 3-31. Serial Interface Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
022
023
024
025
026
SER_CTL
SER_DAT
R/W
R/W
R/W
R/W
R/W
SER_A[6]
SER_DAT[7]
—
SER_A[5]
SER_DAT[6]
—
SER_A[4]
SER_DAT[5]
—
SER_A[3]
SER_DAT[4]
—
SER_A[2]
SER_DAT[3]
—
SER_A[1]
SER_DAT[2]
—
SER_A[0]
SER_DAT[1]
—
SER_RW
SER_DAT[0]
SER_DONE
SER_IER
RT[0]
SER_STAT
SER_CONFIG
RAM Test
SER_CS
RT[7]
SER_CLK
RT[6]
—
—
—
—
—
RT[5]
RT[4]
RT[3]
RT[2]
RT[1]
CONEXANT [ CONEXANT SYSTEMS, INC ]
