3.0 Registers
CX28394/28395/28398
3.9 Receiver Registers
Quad/x16/Octal—T1/E1/J1 Framers
RAIS
Receive Alarm Indication Signal—Criteria for detection and clearance of RAIS per ITU G.775
and ANSI T1.231.
Mode
E1
RAIS
0
Set/Clear Criteria
Cleared if 2 consecutive double frames (500 µs) each
contain 3 or more zeros out of 512 bits or FAS
alignment is recovered [FRED = 0; addr 049].
E1
T1
T1
1
0
1
Set if 2 consecutive double frames each contain 2 or
fewer zeros out of 512 bits and FAS alignment is lost
[FRED = 1; addr 049].
Cleared if data received for a period of 3 ms contains
5 or more zeros out of 4632 bits or frame alignment is
recovered [FRED = 0; addr 049].
Set if data received for a period of 3 ms contains 4 or
fewer zeros out of 4632 bits and frame alignment is
lost [FRED = 1; addr 049].
RALOS
Receive Loss of Signal or Receive Clock—Reports loss of receive clock (RCKI) or loss of
receive signal [RLOS; addr 047] for 1 msec depending on the RALOS configuration bit
[RAL_CON; addr 020].
When set for loss of clock, RALOS becomes active (1) if the receive clock on the RCKI pin
is not present, and inactive (0) if the clock is present.
When set for loss of signal, RALOS indicates that all zeros have been received for at least 1
msec (RLOS is active for 1 msec). This status is provided for compatibility with ITU-I.431
loss of signal detection requirements; and works in conjunction with LIUs which detect loss of
signal if the received signal level falls below a certain threshold and which have a signal
‘squelch’ feature. Operation is as follows:
• The LIU detects receive loss of signal if the receive level falls below:
– 30 dB below nominal for T1.
– 20 dB below nominal for E1
• The LIU squelches (turns off) the signal to the framer so all zeros are received.
• RLOS is reported after 100 continuous zeros are detected.
• RALOS is reported after RLOS is active for 1 msec.
RLOS
Receive Loss of Signal—Criteria for detection and clearance of RLOS per ITU G.775 and
ANSI T1.231.
Mode
T1
RLOS
0
Set/Clear Criteria
Cleared if received data sustains an average pulse
density of 12.5% over a period of 114 bits starting
with the receipt of a pulse, and no occurrence of 100
consecutive zeros.
T1
E1
1
0
Set if 100 consecutive zeros received.
Cleared upon reception of 193 bits in which no
interval of 32 consecutive zeros appear, where the
193-bit window begins with receipt of a pulse.
E1
1
Set upon reception of 32 consecutive zeros.
3-46
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
