3.0 Registers
CX28394/28395/28398
3.9 Receiver Registers
Quad/x16/Octal—T1/E1/J1 Framers
046—Alarm/Error/Counter Latch Configuration (LATCH)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
—
STOP_CNT
LATCH_CNT
LATCH_ERR
LATCH_ALM
STOP_CNT
Stop Error Count during RLOF/RLOS/RAIS—If enabled, error count registers [addr 050–057]
are suspended at their present values during any receive loss of frame (RLOF), loss of signal
(RLOS), or all ones (RAIS) alarm condition. STOP_CNT does not affect counting of test
pattern errors [BERR; addr 058, 059] or alarm events [AERR; addr 05A]. The occurrence of a
red or AIS CGA will inhibit further processing of all other performance parameters (i.e., BER,
errored seconds, SLIPS, etc.). However, a CGA caused by a yellow alarm will not inhibit
further alarm or performance monitoring
0 = continue error count during alarms
1 = stop error count during alarms
LATCH_CNT
Enable ONESEC Latching of Counters—Determines interval for which error counts remain
held in all count registers [addr 050–057]. LATCH_CNT must be active in T1 mode whenever
automatic one-second performance report messaging [AUTO_PRM; addr 0AA] is enabled.
Note that LATCH_CNT active during E1 mode prevents the processor from using RLOF
counter overflow [addr 007] as a 128 ms MFAS timeout.
When LATCH_CNT is inactive, the processor read of the LSB register reports current LSB
error count, it latches current MSB error count to MSB register, and clears LSB. Subsequently,
reading MSB register reports current latched MSB error count and then clears MSB.
LATCH_CNT
Count Latched
Never
Count Hold Time
Until read clear
ONESEC interval
0
1
ONESEC interval
LATCH_ERR
LATCH_ALM
Enable ONESEC Latching of Errors—Determines the interval for which latched active errors
are held in error interrupt [ISR5; addr 006] and pattern interrupt [ISR0; addr 00B] status.
IER
0
LATCH_ERR
ISR Latched
ISR Hold Time
Until read clear
ONESEC interval
Until read clear
0
1
Rising edge event
Rising edge event
Rising edge event
0
1
X
Enable ONESEC Latching of Alarms—Determines interval for which latched active alarms
remain held in alarm interrupt status [ISR7, ISR6; addr 004, 005].
IER
0
LATCH_ALM
ISR Latched
ISR Hold Time
Until read clear
ONESEC interval
Until read clear
0
1
Rising edge or transition
Rising edge or transition
Rising edge or transition
0
1
X
NOTE(S): Interrupt type determines rising edge or transition event.
3-44
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
