CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.10 Performance Monitoring Registers
3.10 Performance Monitoring Registers
If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective Performance Monitoring
counter, the counter is allowed to roll over after reaching its maximum count value. If the overflow interrupt is
disabled, the counter will hold its maximum value upon saturation. Refer also to LATCH [addr 046] for a
description of one-second latched counter operation. Processor must read LSB before reading MSB of each
multi-byte counter.
050—Framing Bit Error Counter LSB (FERR)
7
6
5
4
3
2
1
0
FERR[7]
FERR[6]
FERR[5]
FERR[4]
FERR[3]
FERR[2]
FERR[1]
FERR[0]
FERR[7:0]
Ft/Fs/T1DM/FPS/FAS Error Count
051—Framing Bit Error Counter MSB (FERR)
If LATCH_CNT [addr 046] is inactive, reading FERR [addr 051] clears the entire FERR[11:0] count value.
15
14
13
12
11
10
9
8
0
0
0
0
FERR[11]
FERR[10]
FERR[9]
FERR[8]
FERR[11:8]
Ft/Fs/T1DM/FPS/FAS Error Count
052—CRC Error Counter LSB (CERR)
7
6
5
4
3
2
1
0
CERR[7]
CERR[6]
CERR[5]
CERR[4]
CERR[3]
CERR[2]
CERR[1]
CERR[0]
CERR[7:0]
CRC6/CRC4 Error Count
053—CRC Error Counter MSB (CERR)
If LATCH_CNT [addr 046] is inactive, reading CERR [addr 053] clears the entire CERR[9:0] count value.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
CERR[9]
CERR[8]
CERR[9:8]
CRC6/CRC4 Error Count
100054E
Conexant
3-49
CONEXANT [ CONEXANT SYSTEMS, INC ]
