3.0 Registers
CX28394/28395/28398
3.10 Performance Monitoring Registers
Quad/x16/Octal—T1/E1/J1 Framers
054—Line Code Violation Counter LSB (LCV)
7
6
5
4
3
2
1
0
LCV[7]
LCV[6]
LCV[5]
LCV[4]
LCV[3]
LCV[2]
LCV[1]
LCV[0]
LCV[7:0]
BPV and EXZ (if EXZ_LCV enabled) Error Count
055—Line Code Violation Counter MSB (LCV)
If LATCH_CNT [addr 046] is inactive, reading LCV [addr 055] clears the entire LCV[15:0] count value.
15
14
13
12
11
10
9
8
LCV[15]
LCV[14]
LCV[13]
LCV[12]
LCV[11]
LCV[10]
LCV[9]
LCV[8]
LCV[15:8]
BPV and EXZ (if EXZ_LCV enabled) Error Count
056—Far End Block Error Counter LSB (FEBE)
7
6
5
4
3
2
1
0
FEBE[7]
FEBE[6]
FEBE[5]
FEBE[4]
FEBE[3]
FEBE[2]
FEBE[1]
FEBE[0]
FEBE[7:0]
FEBE Count (applicable only in E1 mode)
057—Far End Block Error Counter MSB (FEBE)
If LATCH_CNT [addr 046] is inactive, reading FEBE [addr 056, 057] clears the entire FEBE[9:0] count value.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
FEBE[9]
FEBE[8]
FEBE[9:8]
FEBE Count (applicable only in E1 mode)
058—PRBS Bit Error Counter LSB (BERR)
Reading BERR transfers the most recent 12-bit count from the internal PRBS error counter to BERR[11:0],
then clears the internal error counter without affecting the reported BERR[11:0] value. Subsequent reads of
BERR MSB [addr 059] report the BERR [11:8] count value latched when BERR LSB was last read.
7
6
5
4
3
2
1
0
BERR[7]
BERR[6]
BERR[5]
BERR[4]
BERR[3]
BERR[2]
BERR[1]
BERR[0]
BERR[7:0]
BERR Count (applicable only for test pattern)
3-50
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
