CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
The BY_PLL bit bypasses the PLL, and the encoder clock will be at the
crystal frequency. This bit takes precedence over the EN_XCLK bit.
The second timing generator controls the generation of the HSYNC*,
VSYNC*, and BLANK* signals, and pixel input clocking. This is normally the
same clock as the encoding clock. The EN_ASYNC register bit, if set, allows this
clock to be driven directly by the CLKI pin. If the DIV2 register bit is set, this
internal clock is divided by two before driving the second timing generator. This
is required for interlaced input to interlaced output mode (i.e., CCIR601/DVD
and CCIR656 applications).
The CLKI pin is the clock used for synchronizing pixel inputs (P[23:0]) with
the timing input signals (HSYNC*, VSYNC*, and BLANK*) and normally is a
delayed version of the CLKO pin. It can be directly connected to CLKO if
desired. Data is registered with this input and re-synchronized to the internal
clock. In a multiplexed input mode, both edges of the CLKI input are used. If the
MODE2X register bit is set, the internal clock is divided by two, allowing a 2x
external clock, and data to be provided on the rising edge only.
1.3.6.1 3:2 Clocking
Mode
All graphics controllers require some finite time for resetting their internal
counters to zero, clearing register flags, and any other event that needs to be
performed on a line-by-line basis. The sum of time these incidents take are the
graphics controller’s Horizontal Blanking Time. The amount of Horizontal
Blanking time varies from one master device to another but it can never be less
than 0 µs and usually does not exceed 4 µs per digital line.
100381B
Conexant
1-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
