1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
If the desired overscan ratio is not available via a particular autoconfiguration
mode, you should derive another 3:2 Solution via Super Cockpit (i.e., CX25870
register programming tool), or contact your local FAE directly. If done correctly,
this CX25870/871 register set will have PLL_32CLK (bit 5 of register 0x38) set
and adjust the timing registers appropriately.
1.3.7 Master, Pseudo-Master, and Slave Interfaces
Like its predecessor, the Bt868/869, the CX25870/871 encoder can be operated in
three possible interfaces. These connection types are named master,
pseudo-master, and slave. The clocking ability of the master device and direction
of the timing signals dictate what particular interface is used between the
Conexant encoder and graphics controller/data master device.
1.3.7.1 Master Interface
In master interface, CLKO, HSYNC*, VSYNC*, and BLANK*, are generated by
the encoder as outputs. These signals’ leading edges denote when a new clock
period, new line, and new frame starts respectively. Because the encoder transmits
the clock and timing signals, this interface is also referred to as clocking
master/timing master.
An illustration of the master interface is shown below using the graphics
controller as the master device and S-Video and two Composite ports as the video
outputs.
Figure 1-5. Operating the CX25870/871 in Master Interface
Clock
Clock
CLKO
Composite #1
Luma
CLKI
Delay
CX25870/
CX25871
S-Video
RGB or
Chroma
Graphics
Controller
YCrCb
Composite #2
HSYNC*
VSYNC*
BLANK*
100381_054
A minimum of 9 inputs (CLKI and 8 lines for pixel data- P[7:0]) and 3 outputs
(HSYNC*, VSYNC*, and CLKO) are required for this configuration. The
amount of inputs could grow as high as 25 if 24-bit RGB nonmultiplexed mode is
chosen as the Input Pixel Mode (i.e., IN_MODE[3:0] = 0011) by the designer.
Master interface can only exist if the graphics controller can accept the
encoder’s reference clock and send back a version of that clock at the same
frequency with the pixel data transitions synchronized to CLKI’s rising and
falling edges. This is accomplished via the VGA encoder’s clock output (CLKO)
and clock input (CLKI) ports.
1-18
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
