CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
1.3.3 Low Voltage Graphics Interface
The CX25870/871 can receive or transmit signals from/to a graphics controller at
any of five different voltage levels. The allowable voltage levels are 3.3 V, 1.8 V,
1.5 V, 1.3 V, and 1.1 V. Default input/output voltage amplitude for the interface
signals (defined as P[23:0], HSYNC*, VSYNC*, CLKI, CLKO, BLANK*, and
FIELD) is 3.3 V and matches the Bt868/869 to ensure backwards compatibility.
For a 3.3 V digital interface, no special configuration steps are necessary.
Simply follow “Recommended Layout for Connection with a 3.3 V Master
Device” in Chapter 3.3 and on power-up, the encoder will automatically expect
3.3 V signal transitions.
For a 1.8 V or lower digital interface, several special configuration steps are
necessary. First, the layout must adhere to Chapter 3.3’s “3.3 V/1.8 V.
Recommended Layout for Connection with a 1.8 V Master Device.” Second,
program the DRVS[1:0] field (bits[6:5] of register (0x32)) to 01(or an alternate
value for 1.5 V, 1.3 V or 1.1 V interface). This forces the encoder to increase its
drive strength on each interface signal used as an output in the interface. Third,
connect the VDDL (pin 40) and VDD_CO (pin 57) power supply pins to the
correct lower supply voltage (1.8 V or other). Fourth, using a voltage divider
circuit or some other method, tie the CX25870/871’s VDD_VREF input (pin 49)
to a level equal to (VDDL/ 2 ). Make sure this voltage source is stable since the
VDDL pin controls the output signal levels. The VDD_VREF pin dictates the
encoder threshold voltage received for the appropriate input signals. The third and
fourth steps are illustrated in Figure 3-5. Make sure the graphics controller is
configured to send and accept signals at the lower supply voltage.
Adjusting VDD_CO, VDDL and VDD_VREF appropriately controls the
input voltage levels for the digital input pins P[23:0], CLKI, and
HSYNC*/VSYNC*/BLANK* (in slave interface; EN_BLANKO = 0). Using the
DRVS[1:0] bits control the output voltage levels for the digital output pins CLKO,
FIELD, and HSYNC*/VSYNC*/BLANK* (in master or pseudo-master interface;
EN_BLANKO = 1). In this way, the digital input pins can operate at different
input voltage levels than the digital output voltage levels.
100381B
Conexant
1-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
