1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.6 Clocking and Timing Generation
Two timing generators control the operation of the encoder. The output encoder
timing block generates the signals for the proper encoding of the video into
NTSC, PAL, or SECAM and extracts the processed input pixels from the internal
FIFO. The encoding timing generator can receive its clock from either an external
crystal oscillator and internal PLL (master and pseudo-master interface), or from
the CLKI pin (slave interface). Conexant recommends that the encoding clock be
generated by the PLL. Register bit EX_XCLK selects the clock source. If
EN_XCLK is set to a logical 0, the internal clock source is selected via the crystal
attached to XTALIN/XTALOUT. When the EN_XCLK bit is set, the clock source
received at the CLKI pin is utilized as the main pixel/encoder clock. Conexant
recommends that the encoding clock be generated by the PLL.
A crystal must be present between XTALIN and XTALOUT pins if the
internal clock source is selected. In this case, the CX25870/871’s CLK frequency
is synthesized by its PLL such that the pixel clock frequency equals
For PLL DIV10=0: Fclk = Fxtal * {PLL_INT(5:0) + [PLL_FRACT(15:0)/216]}/6
For PLL DIV10=1: Fclk = Fxtal * {PLL INT(5:0) + [PLL FRACT(15:0)/216]}/10
where:
Fclk = CLKO Output Frequency = CLKI Input Frequency
NOTE: In some special modes, CLKO = Fclk / 2.
The crystal must be chosen so that the precise line rate for the video standards
required can be achieved. This is done to maintain the subcarrier relationship to
the line rate and thereby achieve the precise subcarrier frequency required. The
crystal oscillator is designed to oscillate from 5 MHz through 25 MHz. A
13.5000 MHz crystal meets the requirements for NTSC, PAL, and SECAM video
standards. The crystal must be within 50 ppm of the maximum desired clock rate
for NTSC operation, and 25 ppm for PAL or SECAM operation, across the
temperature range (0° to 70° C). If the CX25870/871 is to provide all video
outputs selectable through software, the customer must use a crystal with a
maximum tolerance across the temperature range of 25 ppm. Appendix B
contains a list of previously tested and recommended crystal vendors.
The crystal oscillator is disabled by the XTAL _PAD_DIS register bit.
Sufficient time (20 µs) must be allowed after coming out of sleep mode to allow
the oscillator to stabilize. The PLL_LOCK bit is set when the PLL is stable. In
addition, if the PLL_INPUT register bit is set to a logical 1, CLKI is selected as
the reference for PLL. In this special mode (slave interface with the PLL_32CLK
high), the above Fclk formulas replace Fxtal with FCLKI/2 (i.e., input clock
frequency is divided by 2).
If the external clock source is selected (EN_XCLK=1), a clock signal of the
desired pixel clock rate must be present at the CLKI pin. The CLKO pin is
three-stated, and the crystal oscillator disabled. The clock must meet the same
requirements as above. It is highly recommended that the internal clock be used in
order to ensure the output video remains within the specifications defined by the
relevant video standard. Any aberration in the source clock is reflected in the
color subcarrier frequency of the output video and detracts from the quality of the
image on the television.
1-14
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
