CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
1.3.4 Reset
If the RESET* pin is held low (between 0.8 V and GND –0.5 V) for a minimum
of 20 clock cycles, a timing reset and a software reset is performed and the serial
interface is held in the reset condition. A timing reset, which can be generated by
setting the TIMING_RST register bit, will set the subcarrier phase to zero, and
configure the horizontal and vertical counters to the beginning of VSYNC* of
Field 1 (both counters equal to zero).
If the CX25870/871 is in the master interface (i.e., CX25870 sends the syncs
to the data master) then after a power-on or pin reset the encoder and the flicker
filter starts a line 1, pixel 1 of their respective timing generation. For the encoder
this means the odd field is always the first field after a power-on reset, pin reset,
or timing reset.
In timing the slave interface (CX25870 is either pseudo-master or pure slave),
even though the input is receiving progressive frames that have no field
associated with it, the input timing generator keeps track of the frames received.
As a result, after every second frame received, a frame sync is sent to the encoder
section so that the input and encoder remain synchronized. The frame sync forces
the encoder to the beginning of the odd field.
Conexant recommends that after every overscan compensation or video output
type change, the TIMING_RST bit be enabled. The setting of the TIMING_RST
bit should occur after waiting a minimum of 1 ms between the last CX25870
register write for the new overscan compensation ratio. The TIMING_RST
register bit clears itself and reinitializes the internal timing generators.
A software reset, which can be generated by setting the SRESET register bit,
initializes all the serial interface registers to their default state. As a result, all
digital output control pins are three-stated. Registers 0x38 and 0x76 to 0xB4
inclusive are then initialized to auto-configuration mode 0 (see the Auto
Configuration section values) or mode 1 depending on the state of the PAL pin.
The EN_OUT bit must be set to enable the digital outputs.
A power-on reset, pin reset, or timing reset (register 0x6C, bit 7) causes the
input timing generator to send the encoder a frame synchronization pulse setting
the encoder to the beginning of the odd field. The first HSYNC*/VSYNC*
combination then corresponds to the encoder even field and then the second
HSYNC*/VSYNC* combination again causes a frame synchronization pulse and
the encoder will start the odd field, and so on and so forth.
A power-on reset is generated on power-up. The power-on reset generates the
same type of reset as the RESET* pin. A time delay circuit triggered after the
supply voltage reaches a value sufficiently high enough for the circuit to operate
and then generate the power-on reset. As such, the device may not initialize to the
default state unless the power supply ramp rate is sufficiently fast enough. A
hardware/pin reset is recommended if the default state is required.
1.3.5 Device Initialization
After a reset condition, the device must be programmed through the serial
interface to activate a video output and enable the CLKO, HSYNC*, VSYNC*,
and FIELD outputs. The easiest method for accomplishing the initialization phase
is to use one of the auto configuration modes in Appendix C, and program the
interface bits appropriately. (Refer to Section 1.3.8.)
100381B
Conexant
1-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
