2
2.0 Internal Registers
A complete register bit map CX25870/871 is displayed in Table 2-1. All registers are read/write unless denoted
otherwise. For bit descriptions and detailed programming information, follow the register bit map below. All
registers are set to their default state following a software reset. A software reset is always performed at
power-up. After power-up, a reset can be triggered by to writing the SRESET register bit.
Table 2-1. Register Bit Map (* Indicates Read-Only Register) (1 of 4)
8-Bit
Address
D7
D6
D5
D4
D3
D2
D1
D0
*00
ID[2:0]
VERSION[4:0]
*02 MONSTAT_A MONSTAT_B MONSTAT_C CCSTAT_E
CCSTAT_0
FIELD_CNT[2:0]
*04 Reserved
SECAM
PLL_RESET_ PLL_LOCK
OUT
FIFO_OVER FIFO_UNDER PAL
Reserved
*06 MONSTAT_A MONSTAT_B MONSTAT_C MONSTAT_D
FIELD_CNT[3:0]
28
2E
SERIALTEST[7:0]
RPR_SYNC_D GY_SYNC_DIS BPB_SYNC_D HD_SYNC_
HDTV_EN
RGB2PRPB
RASTER_SEL[1:0]
IS
IS
EDGE
30
32
SLEEP_EN XTAL_PAD_
DIS
XTL_BFO_
DIS
PLL_KEEP_
ALIVE
DIS_CLKI
DIS_PLL
DIS_CLKO Reserved
AUTO_CHK
DRVS[1:0]
SETUP_HOLD_A IN_MODE[3] DATDLY_RE OFFSET_
DJ
CSC_SEL
RGB
34
36
ADPT_FF
FFRTN
Reserved
YSELECT
Reserved
C_ALTFF[1:0]
C_THRESH[2:0]
DIV2
Reserved
Y_ALTFF[1:0]
Y_THRESH[2:0]
38(1)
Reserved
PIX_DOUBLE PLL_32CLK
HBURST_
END[8]
HBURST_
BEGINS[8]
V_LINESI
[10]
H_BLANKI
[9]
3A
Reserved
Reserved Reserved
14318_XTAL
HALF_CLKO PLL_DIV10
PLL_INPUT DIV2_
LATCH
3C
3E
40
42
44
46
48
MCOMPY[7:0]
MCOMPU[7:0]
MCOMPV[7:0]
MSC_DB[7:0]
MSC_DB[15:8]
MSC_DB[23:16]
MSC_DB[31:24]
100381B
Conexant
2-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
