CX25870/871
2.0 Internal Registers
Flicker-Free Video Encoder with Ultrascale Technology
2.1 Essential Registers
2.1 Essential Registers
The power-up state will be either autoconfiguration mode 0 (640 x 480 RGB in NTSC out) or autoconfiguration
mode 1 (640 x 480 RGB in, PAL_BDGHI out) depending on the state of the PAL pin. By default, the
CX25870/871 will be in master interface. To enable active video, the EACTIVE register bit must be set.
2.2 Device Address
The serial device address for the CX25870/871 is configurable by the state of the ALTADDR pin at reset.
Table 2-2 lists how the ALTADDR pin switches the devices serial address. The ALTADDR pins state should
only be changed during power-up.
Table 2-2. Serial Address Configuration
ALTADDR State
Device Address for Writing
Device Address for Reading
0
1
0x88
0x8A
0x89
0x8B
2.3 Writing Registers
Following a start condition, writing 0x88 as the device ID initiates write access to the CX25870/871 registers
when the ALTADDR pin is low. Alternative device ID 0x8A initiates write access when the ALTADDR pin is
high. If the data is written sequentially in subaddress order, only the first subaddress needs to be written; the
internal address counter will automatically increment after each write to the next register.
When writing an entirely new register set to the CX25870/871, make sure to skip register 0xB8. This is the
autoconfiguration register, and writing any value to it after having loaded values into other registers will replace
desired data with unwanted data.
100381B
Conexant
2-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
