1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.47 Sleep/Power Management
There are a number of sleep/power down options for the CX25870/871. These
options can be grouped into three different categories. The first category pertains
to power management during normal operation.
•
DIS_PLL bit:
In nonsleep mode, when an external clock is being used, and the PLL is not
needed, this bit will disable the PLL function.
•
XTAL_PAD_DIS bit:
Setting this bit forces the crystal oscillator circuit to completely shut down.
This requires the CX25870/871 to switch over to an external clock or the
RESET* pin needs to be pulsed low to recover.
•
•
XTL_BFO_DIS bit:
This disables the crystal buffer when it is not needed.
DIS_CLKO bit:
This will disable the CLKO output pin when not needed, i.e., an external
clock is used in slave interface or to reduce sleep current.
DACDISx/DACOFF bits:
•
Each individual DAC can be powered down by setting its corresponding
DACDISx bit. This is useful only if some of the DACs are not being
utilized by the graphics system. The entire analog subsection of the device
can be powered-down with the DACOFF bit, allowing digital operations to
continue while reducing the power in the analog circuitry. This will achieve
a significant reduction in power while maintaining all digital functionality.
The second category pertains to software enabled sleep operation.
•
SLEEP_EN bit:
Shuts down all internal clocks except the serial port interface clock.
Disables all digital I/O pins except these: SLEEP, ALTADDR, CLKI,
CLKO, and XTAL_OUT. Disables the PLL. Turns off all DACs and
VREF; SLEEP and RESET* are never disabled.
PLL_KEEP_ALIVE bit:
When the PLL is used to provide a system clock, this bit keeps it
functioning if the rest of the chip is slept through either the sleep pin or
sleep bit. This bit has no affect if DIS_PLL is set.
DIS_CLKI bit:
•
•
The disable for the CLKI is separate from the sleep bit and sleep pin to
accommodate using an external clock as the clock source for the
CX25870/871 or as the PLL input.
The third category relates to the pin driven sleep operation.
•
SLEEP pin:
In addition to what the SLEEP_EN bit does, the sleep pin shuts down the
serial port interface and disables the ALTADDR pin. If the SLEEP pin = 1,
the only way the encoder can return to normal operation is by resetting the
SLEEP pin in 0.
To achieve additional power savings, all the power management options
available in normal operation are also available in software or pin driven sleep
operation.
For the lowest possible power consumption, set the XTL_BFO_DIS,
DIS_CLKO, DIS_CLKI, and XTAL_PAD_DIS bits in order, then pull the SLEEP
pin (#52) high.
1-90
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
