CX11656 HomePlug 1.0 PHY Data Sheet
Figure 3-8. MII Flow Control Overview, Part 1
32 ns
32 ns
(32 bit times)
(32 bit times)
32 ns
MII_CRS
32 ns
(32 bit times)
(32 bit times)
MII_TXEN
MII_TXD[3:1], MII_TX0
Internal TX buffer available pulse
MII_RX[3:0]
P
P
P
P
P
MII_RXDV
External RX buffer available pulse
MII_COL
Case 1
Case 2
Case 3
Case 4
Case 4
TX only
RX only
RX while TX, delayed TX buf avail
RX while no TX buf avail
TX buf avail
102069_012
Figure 3-9. MII Flow Control Overview, Part 2
MII_CRS
MII_TXEN
MII_TXD[3:1], MII_TX0
MII_RX[3:0]
P
P
P
P
MII_RXDV
MII_COL
Case 1
Case 7
Case 8
TX only
TX overrun, frame dropped
Collision
1102069_013
102069A
Conexant Proprietary and Confidential Information
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