CX11656 HomePlug 1.0 PHY Data Sheet
3.1.1.2
MII Signal Descriptions
The following description references Clause 22, Media Independent Interface
specification, used in the 100 Mbps half-duplex mode. The MII is used as a data channel
that transfers data back and forth with flow controlled by the carrier sense signal
(MII_CRS).
MII_TXCLK and MII_RXCLK. The CX11656 generates a stable, continuous 25 MHz
square wave that is supplied on MII_TXCLK and MII_RXCLK. These clocks provide
the timing reference for the transfer of the MII_TXEN and MII_TX signals, as well as
MII_RX, MII_RX_ER, and MII_RXDV.
MII_RX_ER. MII_RX_ER is activated when the CX11656 detects an error in the
receive stream as a result of decoding.
MII_TX_ER. MII_TX_ER is activated by the external host controller when an error
condition is detected during packet transmission. The CX11656 will ignore any MII
transmission within which MII_TX_ER is asserted. MII_TX_ER is ignored if
MII_TXEN is not asserted.
MII_TXEN. MII_TXEN from the external host provides the framing for the Ethernet
packet. An active MII_TXEN indicates to the CX11656 that data on MII_TX[3:0] should
be sampled using MII_TXCLK.
MII_TX[3:0]. MII_TX[3:0] contains the data to be transmitted and transitions
synchronously with respect to MII_TXCLK. MII_TX[0] is the least significant bit. It is
generally assumed that the data will contain a properly formatted Ethernet frame. That is,
the first bits on MII_TX[3:0] correspond to the preamble, followed by SFD and the rest
of the Ethernet frame (DA, SA, length/type, data, CRC).
MII_RXDV. MII_RXDV is asserted by the CX11656 to indicate that the CX11656 has
decoded receive data to present to the external host.
MII_RX[3:0]. MII_RX[3:0] contains the data recovered from the medium by the
CX11656 and transitions synchronously with respect to MII_RXCLK. MII_RX[0] is the
least-significant bit. The CX11656 formats the frame such that the external MAC will be
presented with expected preamble plus SFD.
MII_CRS. MII_CRS is used to tell the external host when the CX11656 is available for
sending a packet. MII_CRS is asynchronous to MII_TXCLK. When a packet is being
transmitted, CRS is held high. CRS will go low whenever the CX11656 is ready to accept
another packet.
On transmit, the CX11656 asserts MII_CRS some time after MII_TXEN becomes active,
and drops MII_CRS after MII_TXEN goes inactive AND when the CX11656 is ready to
receive another packet from the external host for transmission. When MII_CRS has been
negated for at least 900ns, the external MAC may assert MII_TXEN again if there is
another packet to send. This differs from nominal behavior of MII_CRS in that MII_CRS
can extend past the end of the packet by an arbitrary amount of time, while the CX11656
is gaining access to the channel and transmitting the packet. MII_CRS does not affect the
receive side of the channel. Once packets start arriving from the powerline medium and
begin transmission to the external host controller over the MII interface, the external host
must be ready to receive or the packet can be lost. Note that external MACs programmed
to run in 100 Mbps mode do not use a jabber timeout, so there is no timing restriction on
how long MII_CRS can be asserted.
3-6
Conexant Proprietary and Confidential Information
102069A
CONEXANT [ CONEXANT SYSTEMS, INC ]
