CX11656 HomePlug 1.0 PHY Data Sheet
3.1.2.1
MDI Signal Descriptions
Management Data Input/Output
MII_MDIO is a bi-directional signal that is used to transfer status and control information
between the CX11656 and the external host. Control information is driven by the external
host synchronously with respect to MII_MDCLK and is sampled synchronously by the
CX11656. Status information is transferred from the CX11656 to the external host in the
same manner.
Management Data Clock
MII_MDCLK is sourced by the external host as the timing reference for transfer of
information on the MII_MDIO signal.
3.1.3
MII Management Register Set
The IEEE 802.3u mandated management data registers for control and status are
accessible via the Management Data Interface (MDI). These registers are also accessible
via the industry supported serial peripheral interface. The MDI Port will only respond to
addresses 0xbXX000 when the XX field (MSbits of the MDI address) match the state of
the MDI_ADRSEL[1:0] input signals. These registers can also be accessed from the SPI
Slave port when the MDI_SPIS_N select line has been tied low to select the SPI Slave
port.
Table 3-3 summarizes the Power Line Control and Status Register.
The MDI Frame Structure is shown in Figure 3-13.
Table 3-3. Powerline Control and Status Register (PLCSR) Summary
PLCSR
Register Name
Control Register
Status Register
MII Mandated
0
1
X
X
Figure 3-13. MDI Frame Structure
PRE
1...1
1...1
ST
01
01
OP
10
01
PHYAD
AAAAA
AAAAA
RAGAD
RRRRR
RRRRR
TA
Z0
10
Data
Idle
Z
Z
READ
WRITE
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
3.1.3.1
PRE (Preamble)
At the beginning of each MDI transaction, the external host shall send a sequence of 32
contiguous logic “1” bits on the MDIO signal so the CX11656 can establish
synchronization. The CX11656 needs to observe this 32 bit sequence on the MII_MDIO
signal before it responds to any transaction.
3.1.3.2
ST (Start of Frame)
Indicated by a “01” pattern.
3-10
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