CN8478/CN8474A/CN8472A/CN8471A
1.0 System Description
Multichannel Synchronous Communications Controller (MUSYCC™)
1.1 Pin Descriptions
Table 1-4. CN8478 Hardware Signal Definitions (5 of 6)
MQFP
Pin No.
Pin Label
Signal Name
I/O
Definition
80
DEVSEL* PCI Device Select
s/t/s When asserted, DEVSEL* indicates that the driving device has
I/O
I
decoded its address as the target of the current cycle.
60
85
IDSEL
PCI Initialization
Device Select
This input is used to select MUSYCC as the target for
configuration read or write cycles.
SERR*
System Error
o/d O Any PCI device can assert SERR* to indicate a parity error on the
address cycle or parity error on the data cycle of a special cycle
command or any other system error where the result will be
catastrophic. MUSYCC only asserts SERR* if it detects a parity
error on the address cycle.
Since SERR* is not an s/t/s signal, restoring it to the
deasserted state is done with a weak pullup (same value as used
for s/t/s).
MUSYCC does not input SERR*. It is assumed that the host
will reset MUSYCC in the case of a catastrophic system error.
84
PERR*
Parity Error
s/t/s PERR* is asserted by the agent receiving data when it detects a
I/O
parity error on a data phase. It is asserted one clock after PAR is
driven, which is two clocks after the AD and CBE* parity was
checked.
MUSYCC generates the PERR Interrupt Descriptor toward the
host under the following conditions:
•
•
MUSYCC masters a PCI cycle.
After supplying data during the data phase of the cycle,
MUSYCC detects this signal being asserted by the agent
receiving the data.
•
MUSYCC asserts the PCI read cycle and generates the
PERR Interrupt Descriptor toward the host under the
following conditions:
•
•
MUSYCC masters a PCI read cycle.
After receiving the data during the data phase of the
cycle, MUSYCC calculates that a parity error has
occurred.
41
40
47
46
INTA*
INTB*
REQ*
GNT*
PCI MUSYCC
Interrupt
o/d O INTA* is driven by MUSYCC to indicate a MUSYCC Layer 2
interrupt condition to the host processor.
PCI Expansion Bus
Interrupt
o/d O INTB* is driven by MUSYCC to notify the host processor of an
interrupt pending from the EBUS.
PCI Bus Request
t/s O MUSYCC drives REQ* to notify the PCI arbiter that it desires to
master the bus. Every master in the system has its own REQ*.
PCI Bus Grant
I
The PCI bus arbiter asserts GNT* when MUSYCC is free to take
control of the bus, assert FRAME*, and execute a bus cycle.
Every master in the system has its own GNT*.
98
M66EN
66 MHz Enable
I
When asserted, M66EN indicates the system is operating at a
66 MHz PCI clock rate. Otherwise, it is operating at a 33 MHz or
less clock rate. This pin is a no-connect on Revision A and B
devices.
100660E
Conexant
1-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
