1.0 System Description
CN8478/CN8474A/CN8472A/CN8471A
1.1 Pin Descriptions
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 1-4. CN8478 Hardware Signal Definitions (4 of 6)
MQFP
Pin No.
Pin Label
Signal Name
PCI Address
I/O
Definition
48-51,54,
56-58,61,
65-66,
AD[31:0]
t/s I/O AD[31:0] is a multiplexed address/data bus. A PCI transaction
consists of an address phase during the first clock period
followed by one or more data phases. AD[7:0] is the LSB.
and Data
69-72,88,
90-94,97,
99,
101-103,
105-109
43
PCLK
PCI Clock
PCI Reset
I
I
PCLK provides timing for all PCI transitions. All PCI signals
except PRST*, INTA*, and INTB* are synchronous to PCLK and
are sampled on the rising edge of PCLK. MUSYCC supports a
PCI clock up to 66 MHz.
45
PRST*
This input resets all functions on MUSYCC.
59, 74,
87, 100
CBE[3:0]* PCI Command
and Byte Enables
t/s I/O During the address phase, CBE[3:0]* contain command
information; during the data phases, these pins contain
information denoting which byte lanes are valid.
PCI commands are defined as follows:
CBE[3:0]
0000b
Command Type
Interrupt Acknowledge
Special Cycle
Oh
1h
6h
7h
Ah
Bh
Ch
Dh
Eh
Fh
0001b
0110b
0111b
1010b
1011b
1100b
1101b
1110b
1111b
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
86
75
PAR
PCI Parity
PCI Frame
t/s I/O The number of 1s on PAR, AD[31:0], and CBE[3:0]* is an even
number. PAR always lags AD[31:0] and CBE* by one clock.
During address phases, PAR is stable and valid one clock after
the address; during the data phases it is stable and valid one
clock after TRDY* on reads and one clock after IRDY* on writes.
It remains valid until one clock after the completion of the data
phase.
FRAME*
s/t/s FRAME* is driven by the current master to indicate the beginning
I/O
and duration of a bus cycle. Data cycles continue as FRAME*
stays asserted. The final data cycle is indicated by the
deassertion of FRAME*. For a non-burst, one-data-cycle bus
cycle, this pin is only asserted for the address phase.
76
79
83
IRDY*
TRDY*
STOP*
PCI Initiator Ready
PCI Target Ready
PCI Stop
s/t/s IRDY* asserted indicates the current master’s readiness to
I/O complete the current data phase.
s/t/s TRDY* asserted indicates the target’s readiness to complete the
I/O current data phase.
s/t/s STOP* asserted indicates the selected target is requesting the
I/O master to stop the current transaction.
1-22
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
