2.0 Circuit Description
2.7 Transmit System Bus
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
2.7 Transmit System Bus
The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling
buffer, and transmit framer (Figure 2-23). It provides a high-speed serial interface
between the XMTR and system bus. The system bus is compatible with the Mitel
ST-Bus, the PEB Bus, and the AT&T CHI Bus. TSB directly interfaces to other
Conexant devices with no need for external circuitry.
Figure 2-23. TSB Interface Block Diagram
From CLADO Prior to
Output Buffer
CLADO
CLADI
Remote
Channel Channel
Loopback Loopback
Local
RSBCKI
TSBCKI
I/O from Pins
TFSYNC
TMSYNC
TINDO
TSB
Timebase
From
TPHASE
Transmitter
Transmit
Framer
TXDATA
TSLIP
TPCMI
TSIGI
TNRZ
Buffer
TSIG
Buffer
TSIG
Local
The TSB contains the following six pins: Transmit System Bus Clock
(TSBCKI), Transmit PCM Data (TPCMI), Transmit Signaling Data (TSIGI),
Transmit Frame Sync (TFSYNC), Transmit Multiframe Sync (TMSYNC), and
Transmit time slot Indicator (TINDO). See Figure 2-24 for the relationship
between these signals. These pins are further defined in Table 1-1, Hardware
Signal Definitions.
2-46
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
