2.0 Circuit Description
2.6 Clock Rate Adapter
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
JCLK and CLADO are locked to the selected timing reference. The reference
frequency can operate at T1 or E1 line rates, or at any rate supported by the clock
rate adapter. See RSCALE[2:0] [addr 092] to select timing reference frequency.
See Table 2-6 for the JCLK/CLADO timing reference.
Table 2-6. JCLK/CLADO Timing Reference
CEN JEN JFREE JDIR
CLADO/JCLK Reference
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
X
0
REFCKI—Free running 10 MHz clock
0
REFCKI—Free running 10 MHz clock with transmit JAT
REFCKI—Free running 10 MHz clock with receive JAT
TXCLK—TCKI or ACKI per [AISCLK; addr 068]
RXCLK—RPLL or RCKI per [RDIGI; addr 020]
CLADI—System clock bypass JAT elastic store
CLADI—System clock with transmit JAT
0
1
0
0
0
1
1
X
0
1
1
1
CLADI—System clock with receive JAT
NOTE(S):
1. JCLK always operates at T1 or E1 line rate selected by [T1/E1N; addr 001]
CLAD output jitter meets jitter generation requirements of AT&T TR62411,
as listed in Table 2-7.
Table 2-7. Jitter Generation Requirements
Filter Applied
Maximum Output Jitter
Measured
None (Broadband)
10 Hz to 40 kHz
8 kHz to 40 kHz
10 Hz to 8 kHz
0.05 UI peak-peak
0.025 UI peak-peak
0.025UI peak-peak
0.02UI peak-peak
.015 UI
.015 UI
.015 UI
.015 UI
CLAD modes are selected using the Clock Rate Adapter Configuration
register [CLAD_CR; addr 090], the Clock Rate Adapter Frequency Select
[CSEL; addr 091], and the Clock Rate Adapter Phase Detector Scale Factor
[CPHASE; addr 092].
If the CLAD Phase Detector (CPHASE) is disabled [CEN; addr 090], the
CLAD input timing reference is determined by the JEN and JFREE bits
(addr 002).
If the CLAD Phase Detector is enabled [CEN; addr 090], the CLAD input
timing reference is selected using CLADI[1:0] in the Clock Input Mux register
[CMUX; addr 01A]. The input timing reference can consist of the Clock Rate
Adapter Input Pin (CLADI); the Receive Clock Output (RCKO, prior to the
output buffer); the Transmit Clock Input Pin (TCKI); or the Transmit System Bus
Clock Input Pin (TSBCKI). (See Figures 2-21 and 2-22 for more details.)
2-42
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
