Bt8370/8375/8376
2.0 Circuit Description
2.7 Transmit System Bus
Fully Integrated T1/E1 Framer and Line Interface
Figure 2-24. Transmit System Bus Waveforms
TSBCKI
Frame 48 TS 31
Frame 1TS 0
TPCMO
TINDO
TSIGI
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
E1
T1
X
1
X
X
X
A
5
B
6
C
7
D
8
X
F
X
1
X
X
A
4
B
5
C
6
D
7
X
8
X
1
Frame 48 TS 24
Frame 0 TS 1
TPCMI
TINDO
2
3
4
2
3
X
X
X
X
A
B
C
D
X
X
X
X
X
A
B
C
D
X
TSIGI
TFSYNC
TMSYNC
The TSB supports five system bus rates (MHz): 1.536, 1.544, 2.048, 4.096,
and 8.192. The T1 rate, with 24 time slots and without framing bits, is
1.536 MHz. The T1 rate with framing bits is 1.544 MHz. The E1 rate, with
32 time slots, is 2.048 MHz. The 4.096 MHz rate is twice the E1 rate, with
64 time slots. The 8.192 MHz rate is 4 times the E1 rate, with 128 time slots.
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B, C,
and D), of which 1 bus member is selected by the SBI [3:0] bits in the System Bus
Interface Configuration register [SBI_CR; 0D0]. See Figures 2-25 and 2-25.
The system bus rate is independent of the line rate and must be selected using the
System Bus Interface Configuration register.
Figure 2-25. TSB 4.096 MHz Bus Mode Time Slot Interleaving
TSBCKI
TPCMI
TS31A
TS31B
TS0A
TS0B
TSIGI
SIG31A
SIG31B
SIG0A
SIG0B
TFSYNC
NOTE(S): A and B time slot data comes from different Bt8370s. TSBCKI can be operated at 1 or 2 times the data rate.
Figure 2-26. TSB 8.192 MHz Bus Mode Time Slot Interleaving
TSBCKI
TPCMI
TSIGI
TS31A
TS31B
TS31C
TS31D
TS0A
TS0B
TS0C
TS0D
SIG31A
SIG31B
SIG31C
SIG31D
SIG0A
SIG0B
SIG0C
SIG0D
TFSYNC
NOTE(S): A, B, C, and D time slot data comes from different Bt8370s. TSBCKI can be operated at 1 or 2 times the data rate.
N8370DSE
Conexant
2-47