Bt8370/8375/8376
2.0 Circuit Description
2.7 Transmit System Bus
Fully Integrated T1/E1 Framer and Line Interface
In Normal mode, the slip buffer total depth is two 193-bit frames (T1), or two
256-bit frames (E1). Data is written to the slip buffer using TSBCK and read from
the slip buffer using TXCLK. If there is a slight rate difference between the two
clocks, the slip buffer changes from its initial condition—approximately half
full—by either adding or removing frames. If TSBCK writes to the slip buffer
faster than TCKI reads the data, the buffer becomes full. When the slip buffer in
Normal mode is full, an entire frame of data is deleted. Conversely, if TXCLK is
reading the slip buffer at a faster rate than TSBCK is writing the data, the buffer
eventually empties. When the slip buffer in Normal mode is empty, an entire
frame of data is duplicated. When an entire frame is deleted or duplicated, it is
known as a Frame Slip (FSLIP). An FSLIP is always 1 full frame of data. The
FSLIP status is reported in the Slip Buffer Status register [SSTAT; addr 0D9].
In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial
throughput delay is 32 bits, or half of the total depth. Similar to Normal mode,
Elastic mode allows the system bus to operate at any of the programmable bus
rates, independent of the line rate. The advantage of this mode over the
Two-Frame mode is that throughput delay is reduced from 1 frame to an average
of 32 bits, and the transmit multiframe can retain its alignment with respect to the
transmit data. The disadvantage of this mode is handling the full and empty buffer
conditions. In 64-bit Elastic mode, an empty or full buffer condition causes an
Uncontrolled Slip (USLIP). Unlike an FSLIP, a USLIP is of unknown size,
ranging from 1 to 256 bits of data. The USLIP status is reported in SSTAT.
The Two-Frame Short mode combines the depth of the Normal mode with the
throughput delay of the Elastic mode. This mode begins in Elastic mode with a
32-bit initial throughput delay, and switches to Normal modes when the buffer is
empty or full; thereafter, the Two-Frame Short and Normal modes perform
identically. If the slip buffer is full (two frames) in the Two-Frame Short and
Normal modes, an FSLIP is reported; thereafter, the slip buffer performs exactly
like Normal mode.
In Bypass mode, data is clocked through TSLIP from the TSB to the XMTR
using TXCLK as selected by the TCKI input clock mux.
2.7.3 Signaling Buffer
The 32-byte Transmit Signaling Buffer [TSIG; addr 120–13F] stores a single
multiframe of signaling data input from the TSIGI pin and is updated as each time
slot is received in every TSB frame. Each byte offset into TSIG represents a
different time slot for signaling data: offset 0 stores TS0 signaling data, offset
1 stores TS1 signaling data, and so on. The signaling data is stored in the least
significant 4 bits of the signaling buffer. Similar to TSLIP, TSIG has read/write
processor access for accessing or overwriting signaling information. The signaling
buffer uses TFSYNC to identify the frame boundaries in the TSIGI data stream.
N8370DSE
Conexant
2-49
CONEXANT [ CONEXANT SYSTEMS, INC ]
