3.18Regis
Table 3-28. Primary Control and Status Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
r
7
6
5
4
3
2
1
0
r
014
015
016
017
018
019
01A
01B
01C
LOOP
DL3_TS
DL3_BIT
FSTAT
PIO
R/W
R/W
R/W
R
—
DL3EN
DL3_BIT[7]
—
—
FS[1]
DL3_BIT[6]
—
—
FS[0]
—
PLOOP
TS[3]
LLOOP
TS[2]
FLOOP
TS[1]
ALOOP
TS[0]
TS[4]
DL3_BIT[5]
—
DL3_BIT[4]
INVALID
INDY_IO
RDL_OE
TSBCKI[0]
TMUX[4]
—
DL3_BIT[3]
FOUND
DL3_BIT[2]
TIMEOUT
RMSYNC_IO
TCKO_OE
CLADI[0]
TMUX[2]
—
DL3_BIT[1]
ACTIVE
DL3_BIT[0]
RX/TXN
R/W
R/W
R/W
R/W
R/W
ONESEC_IO
—
RDL_IO
—
TDL_IO
TDL_OE
TSBCKI[1]
TMUX[5]
—
RFSYNC_IO
INDY_OE
CLADI[1]
TMUX[3]
—
TFSYNC_IO
CLADO_OE
TCKI[1]
TMSYNC_IO
RCKO_OE
TCKI[0]
POE
CMUX
TMUX
TEST
RSBCKI[1]
—
RSBCKI[0]
—
TMUX[1]
TEST[1]
TMUX[0]
TEST[0]
—
—
Table 3-29. Receive LIU Registers (1 of 2)
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
020
021
022
023
024
025
026
LIU_CR
RSTAT
R/W
R
RST_LIU
CPDERR
FRZ_SHORT
—
SQUELCH
JMPTY
HI_CSLICE
LPF[6]
FORCE_VGA
ZCSUB
RDIGI
EXZ
ATTN[1]
BPV
ATTN[0]
—
—
1
EYEOPEN
RLB0
PRE_EQ
RLIU_CR
LPF
R/W
R/W
R/W
R/W
R/W
AGC[1]
AGC[0]
EQ_FRZ
OOR_BLOCK
LPF[2]
LONG_EYE
LPF[0]
LPF[5]
LPF[4]
LPF[3]
LPF[1]
VGA_MAX
EQ_DAT
EQ_PTR
—
—
VGA_MAX[5]
EQ_DAT[5]
EQ_PTR[5]
VGA_MAX[4]
EQ_DAT[4]
EQ_PTR[4]
VGA_MAX[3]
EQ_DAT[3]
EQ_PTR[3]
VGA_MAX[2]
EQ_DAT[2]
EQ_PTR[2]
VGA_MAX[1]
EQ_DAT[1]
EQ_PTR[1]
VGA_MAX[0]
EQ_DAT[0]
EQ_PTR[0]
EQ_DAT[7]
—
EQ_DAT[6]
—
CONEXANT [ CONEXANT SYSTEMS, INC ]
