Table 3-26. Interrupt Status Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
004
005
006
007
008
009
00A
00B
ISR7
ISR6
ISR5
ISR4
ISR3
ISR2
ISR1
ISR0
R
R
R
R
R
R
R
R
RMYEL
LOOPDN
TSLIP
FRED[4]
TSIG
RYEL
LOOPUP
RSLIP
RPDV
TPDV
RAIS
TSHORT
JERR
RALOS
TLOC
RLOS
—
RLOF
TLOF
SIGFRZ
ONESEC
FERR
CKERR
SEF[2]
TMF
CERR
SERR
MERR
COFA[2]
TMSYNC
RFULL1
RFULL2
—
BERR[12]
TFRAME
RMSG1
RMSG2
PSYNC
FEBE[10]
RSIG
LCV[16]
RMSYNC
TEMPTY1
TEMPTY2
TSERR
CRC[10]
RMF
FERR[12]
RFRAME
TMSG1
TMSG2
TFERR
TBOP
RNEAR1
RNEAR2
BSLIP
TDLERR1
TDLERR2
TCERR
TNEAR1
TNEAR2
TMERR
RBOP
—
Table 3-27. Interrupt Enable Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
00C
00D
00E
00F
010
011
012
013
IER7
IER6
IER5
IER4
IER3
IER2
IER1
IER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RMYEL
LOOPDN
TSLIP
LOF
RYEL
LOOPUP
RSLIP
RPDV
TPDV
CKERR
SEF
RAIS
TSHORT
JERR
RALOS
TLOC
RLOS
—
RLOF
TLOF
SIGFRZ
ONESEC
FERR
CERR
SERR
MERR
CRC
COFA
BERR
FEBE
LCV
FERR
TSIG
TMSYNC
RFULL1
RFULL2
—
TMF
TFRAME
RMSG1
RMSG2
PSYNC
RSIG
RMSYNC
TEMPTY1
TEMPTY2
TSERR
RMF
RFRAME
TMSG1
TMSG2
TFERR
TBOP
RBOP
—
RNEAR1
RNEAR2
BSLIP
TDLERR1
RDLERR2
TCERR
TNEAR1
TNEAR2
TMERR
.
8
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