3.18Regis
Table 3-36. CLAD Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
r
7
6
5
4
3
2
1
0
090
091
092
093
CLAD_CR
CSEL
R/W
R/W
R/W
R/W
CEN
VSEL[3]
—
XSEL[2]
VSEL[2]
RSCALE[2]
—
XSEL[1]
VSEL[1]
RSCALE[1]
—
XSEL[0]
VSEL[0]
RSCALE[0]
PNSEL
LFGAIN[3]
OSEL[3]
—
LFGAIN[2]
OSEL[2]
VSCALE[2]
TBUS
LFGAIN[1]
OSEL[1]
VSCALE[1]
RWINI
LFGAIN[0]
OSEL[0]
VSCALE[0]
JINIT
a
CPHASE
CTEST
—
D20A
Table 3-37. Bit-Oriented Protocol Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
0A0
0A1
0A2
0A3
BOP
TBOP
R/W
R/W
R
RBOP_START
—
RBOP_INTEG
—
RBOP_LEN[1]
TBOP[5]
RBOP[5]
—
RBOP_LEN[0]
TBOP[4]
RBOP[4]
—
TBOP_LEN[1]
TBOP[3]
RBOP[3]
—
TBOP_LEN[0] TBOP_MODE[1] TBOP_MODE[0]
TBOP[2]
RBOP[2]
—
TBOP[1]
RBOP[1]
—
TBOP[0]
RBOP[0]
—
RBOP
RBOP_LOST
RBOP_VALID
BOP_STAT
R
TBOP_ACTIVE RBOP_ACTIVE
Table 3-38. Data Link Registers (1 of 2)
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
0A4
0A5
0A6
0A7
DL1_TS
DL1_BIT
DL1_CTL
RDL1_FFC
R/W
R/W
R/W
R/W
DL1_TS[7]
DL1_BIT[7]
—
DL1_TS[6]
DL1_BIT[6]
—
DL1_TS[5]
DL1_BIT[5]
—
DL1_TS[4]
DL1_BIT[4]
TDL1_RPT
FFC[4]
DL1_TS[3]
DL1_BIT[3]
DL1[1]
DL1_TS[2]
DL1_BIT[2]
DL1[0]
DL1_TS[1]
DL1_BIT[1]
TDL1_EN
FFC[1]
DL1_TS[0]
DL1_BIT[0]
RDL1_EN
FFC[0]
MSG_FILL[1]
EOM[1]
MSG_FILL[0]
EOM[0]
FFC[5]
FFC[3]
FFC[2]
RDL1_CNT[5]
RDL1[5]
—
RDL1_CNT[4]
RDL1[4]
RDL1_CNT[3]
RDL1[3]
RDL1_CNT[2]
RDL1[2]
RDL1_CNT[1]
RDL1[1]
RDL1_CNT[0]
RDL1[0]
0A8
RDL1
R
RDL1[7]
—
RDL1[6]
—
0A9
RDL1_STAT
PRM
R
RMSG1
RSTAT1
RMPTY1
RNEAR1
RFULL1
0AA
R/W
AUTO_PRM
PRM_CR
PRM_R
PRM_U1
PRM_U2
PRM_SL
AUTO_SL
SEND_PRM
CONEXANT [ CONEXANT SYSTEMS, INC ]
