Bt8370/8375/8376
3.17 System Bus Registers
Fully Integrated T1/E1 Framer and Line Interface
RLOCAL
Enable Local Signaling Output—Determines whether the RSIGO output signaling and
RPCMO inserted signaling [INSERT; addr 0E0-0FF] are supplied from the RSIGn output
buffer or processor-supplied local signaling from RSIGA–RSIGD.
0 = RSIGn buffer signaling
1 = RSIGA-RSIGD local signaling
RSIGA–RSIGD
Local Receive Signaling—When RLOCAL is active, these four bits are inserted into RSIGO
instead of the buffered signaling from RSIGn. If both RLOCAL and INSERT are active, they
are also inserted into RPCMO during system bus signaling frames.
0 = output signaling bit equals 0
1 = output signaling bit equals 1
1A0–1BF—Receive Signaling Buffer (RSIGn; n = 0 to 31)
The Receive Signaling Buffer (RSIGn) contains all ABCD signaling inputs from all channels, regardless of
whether signaling is active [SIG_STK; addr 180–19F]. RSIGn is not updated during signaling freeze
conditions, or when the receive framer is configured in a non-signaling mode. Normal signaling buffer
operation transfers ABCD input to ABCD output, coincident with the D-bit update (in T1 mode), or coincident
with the receipt of the respective channel's ABCD signaling during TS16 (in E1 mode). When DEBOUNCE is
active, output signaling for active channels is updated coincident with the sampling of each input signaling bit.
This may cause the buffered output value to transition in the middle of the received multiframe.
7
6
5
4
3
2
1
0
RSIGn[7]
RSIGn[6]
RSIGn[5]
RSIGn[4]
RSIGn[3]
RSIGn[2]
RSIGn[1]
RSIGn[0]
RSIGn[7]
Output Signaling A Bit
Output Signaling B Bit
Output Signaling C Bit
Output Signaling D Bit
RSIGn[6]
RSIGn[5]
RSIGn[4]
RSIG0 (E1) RSIG16 (E1 Mode)
RSIGn[3]
RSIGn[2]
RSIGn[1]
RSIGn[0]
Input Signaling A Bit
Input Signaling B Bit
Input Signaling C Bit
Input Signaling D Bit
MAS.1
MAS.2
MAS.3
MAS.4
X.1
MYEL
X.3
X.4
3-134
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
