Bt8370/8375/8376
3.17 System Bus Registers
Fully Integrated T1/E1 Framer and Line Interface
0DA—Receive Signaling Stack (STACK)
STACK contains new signaling information from those channels with SIG_STK [addr 180–19F] enabled.
STACK allows the processor to monitor only changed ABCD signaling values from the selected channels.
RSIG interrupt [addr 008] is triggered at the end of any multiframe where one or more ABCD signaling values
have changed. The processor reads the STACK address twice to retrieve the channel number (Word 0) and to
retrieve the new ABCD value (Word 1). The processor continues to read from STACK until empty. An empty
Stack is indicated when either MORE = 0 in Word 1 or no Word 1 exists (the last two STACK reads are Word 0).
Internal STACK read/write pointers are initialized by RESET [addr 001]. STACK contents are updated for
each channel in which the stack is enabled [SIG_STK; addr 180–19F]. STACK contents are updated with new
output signaling if the buffered RSIGn input and output ABCD signaling values differ. STACK is evaluated on a
channel-by-channel basis after the D-bit is updated. The processor must poll the RSIG interrupt to determine
when STACK has new information.
Word 0: Channel Number (first read)
7
6
5
4
3
2
1
0
WORD
MORE
—
CH[4]
CH[3]
CH[2]
CH[1]
CH[0]
WORD
Stack Word ID (always 0 in Word 0)
MORE
More Stack Contents (always 1 in Word 0)
CH[4:0]
Channel Number (E1 range 0–31; T1 range 1–24)
Word 1: New Signaling Value (second read)
7
6
5
4
3
2
1
0
WORD
MORE
—
—
SIG_BITA
SIG_BITB
SIG_BITC
SIG_BITD
WORD
Stack Word ID (always 1 in Word 1)
WORD
MORE
MPU Response
First word, get channel
Never used
0
0
1
1
0
1
0
1
No change or last change, stop
New signaling, keep reading
MORE
More Stack Contents equals 1 if more available.
SIG_BITA–D
Signaling Bit A–D—Processor reads new ABCD signaling value from this location. The
ABCD value is also present in RSIGn (addr 1A0–1BF) output signaling buffer, so the
processor need not store a local copy of each channel’s signaling status.
3-126
Conexant
N8370DSE