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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
3.17 System Bus Registers  
Fully Integrated T1/E1 Framer and Line Interface  
Signaling State During Current Multiframe  
Signaling State Updated at the End of Current Multiframe  
New Input  
Signaling Bit  
Buffered Input  
Signaling Bit  
from Previous  
Multiframe  
Buffered Output  
Signaling Bit  
(RSIGn[7:4])  
Buffered Input  
Signaling Bit is  
Updated from Input  
Signaling  
Buffered Output  
Signaling Bit  
(RSIGn[7:4])  
Notes  
(RSIGn[3:0])  
Bit (RSIGn[3:0])  
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
Change Output  
Debounce  
Change Output  
Debounce  
NOTE(S): Non-Debounced signaling always transfers buffered ABCD input to buffered ABCD output coincident with the  
D-bit update.  
FRZ_OFF/FRZ_ON Manual Signaling Update and SIGFRZ OutputAllows the processor to manually control  
updates of the receive signaling buffer [RSIGn; addr 1A01BF], the signaling stack [addr  
0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pins output  
state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. The  
receive ABCD input signaling is placed into the STACK and RSIG buffers according to the  
modes shown below. Stack updates are individually enabled on a per-channel basis according  
to SIG_STK [addr 18019F].  
SIGFRZ  
FRZ_ON FRZ_OFF SIG_STK  
Interrupt  
Pin  
0
STACK  
No update  
RSIGn  
0
0
0
0
0
1
1
0
0
X
1
0
1
All ABCD  
No update  
All ABCD  
All ABCD  
All ABCD  
No Update  
1
No update  
0
0
0
ABCD Changes  
No Update  
X
X
1
0
X
X
X
0
1
0
ABCD Changes  
No update  
X
1
THRU  
Enable Transparent Robbed-Bit SignalingRMSYNC is forced to align with respect to RX  
timebase and follow each change of receiver's multiframe alignment, plus any frame offset  
caused by RSLIP buffer delay. In this manner, RMSYNC is able to retain its signaling  
multiframe alignment with respect to RPCMO output data frames. THRU mode is required  
when RSLIP is configured in Bypass mode. It is also useful for ADPCM transcoder systems  
that utilize robbed-bit signaling during frames other than normal (modulo 6) signaling frames,  
and therefore cannot utilize RPCMO signaling reinsertion in ADPCM coded channels. During  
THRU mode, RMSYNC must be programmed as an output [PIO; addr 018]. RMSYNC can  
follow a change of RX multiframe alignment without generating an alarm indication (e.g.,  
receiver change of SF alignment without accompanying loss of basic frame alignment).  
0 = no effect  
1 = transparent robbed-bit signaling  
3-122  
Conexant  
N8370DSE  
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