Bt8370/8375/8376
3.17 System Bus Registers
Fully Integrated T1/E1 Framer and Line Interface
TFSLIP
Controlled TSLIP Event—TUSLIP and TFSLIP event status are latched active-high when
transmit slip error is detected. Either event reports a TSLIP error in ISR5 [addr 006].
Active-high hold interval is defined by LATCH_ERR [addr 046].
Two types of errors are detected:
1. FSLIP = Controlled ±frame slip on TX data output. FSLIP affects transmit
time slot data, but does not change the transmit timebase or frame
alignment.
2. USLIP = Uncontrolled ±1 to ±256 bit slip on TX data. USLIP affects both
time slot data and frame alignment. TUSLIP and TFSLIP status depends
on the transmit system bus configuration [TSB_CR; addr 0D4].
TSBI Mode
Normal
TUSLIP
TFSLIP
TSLIP Event
0
0
0
1
none
FSLIP
1
0
USLIP
1(1)
1
Both FSLIP and USLIP
Short
0
0
none
FSLIP
USLIP
none
0
1
1
0
Elastic
Bypass
0
N/A
N/A
N/A
1
USLIP
—
N/A
NOTE(S):
(1)
Most recent slip error direction is reported in TSDIR.
2. TFSLIP not applicable (read zero value) if TSLIP bypassed or configured as elastic
store. TUSLIP not applicable if TSLIP bypassed. In Short-Delay mode, if the bus
clock is faster than the receive clock, the system bus resynchronizes and USLIP is be
reported. If the receive clock is faster, RSLIP reverts to Normal mode and reports
FSLIP errors.
TUSLIP
RSDIR
Uncontrolled TSLIP Event—See TFSLIP description.
Receive Slip Direction—RSDIR is updated each time an RSLIP error is latched in RFSLIP or
RUSLIP, and indicates which direction the slip occurred.
0 = RSLIP error deleted 1 frame on RPCMO or SBI resync detected
1 = RSLIP error repeated 1 frame on RPCMO or SBI time slot reassigned
3-124
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
