3.0 Registers
Bt8370/8375/8376
3.6 Primary Control and Status Registers
Fully Integrated T1/E1 Framer and Line Interface
018—Programmable Input/Output (PIO)
7
6
5
4
3
2
1
0
ONESEC_IO
RDL_IO
TDL_IO
INDY_IO
RFSYNC_IO
RMSYNC_IO
TFSYNC_IO
TMSYNC_IO
ONESEC_IO
Bidirectional ONESEC Input/Output mode—Selects input or output mode for ONESEC signal
pin, and controls the internal timer interval used for 1-second status latching [LATCH; addr
046]. When ONESEC is an output, the JAT reference clock [JCLK; addr 002] develops the
1-second timer interval output, with an arbitrarily defined initial starting location. When
ONESEC is an input, the timer/latch interval is aligned to the rising edge of ONESEC input.
The system can apply ONESEC input to define any length timer/latch interval up to but not
greater than 1-second.
0 = ONESEC input
1 = ONESEC output
RDL_IO
TDL_IO
Enable Receive Data Link—Selects which signals are present on bi-modal RNEGO/RDLCKO
and RPOSO/RDLO pins. When active, receive data link pins RDLCKO and RDLO are
enabled [see also DL3EN; addr 015]; otherwise, dual-rail RLIU data is output on RNEGO and
RPOSO pins.
0 = RNEGO and RPOSO
1 = RDLCKO and RDLO
Enable Transmit Data Link—Selects which signals are present on bi-modal TNEGI/TDLCKO
and TPOSI/TDLI pins. When active, transmit data link pins TDLCKO and TDLI are enabled
[see also DL3EN; addr 015]; otherwise, TLIU data is supplied by the dual-rail TNEGI and
TPOSI inputs.
0 = TNEGI and TPOSI signals
1 = TDLCKO and TDLI signals
NOTE:
TDL_IO must be programmed to 1 to enable data output from the transmit frame
formatter.
INDY_IO
Enable Time Slot Indicators—Selects which signals are present on bi-modal TNEGO/RINDO
and TPOSO/TINDO pins. When active, system bus time slot indicators RINDO and TINDO
are enabled (see also [SBCn; addr 0E0–0FF]); otherwise, dual-rail TLIU data is output on
TNEGO and TPOSO pins.
0 = TNEGO and TPOSO
1 = RINDO and TINDO
3-32
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
