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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Registers  
Bt8370/8375/8376  
3.6 Primary Control and Status Registers  
Fully Integrated T1/E1 Framer and Line Interface  
ALOOP  
Enable Local Analog LoopbackBipolar data from XTIP/XRING is internally connected to  
RTIP/RRING inputs. Externally applied data on RTIP/RRING inputs is ignored.  
XTIP/XRING output data is unaffected. After ALOOP activation or deactivation, the  
processor must reset the receive line interface [RST_LIU; addr 020]. If RCKO is selected as  
the TCKI clock source [CMUX; addr 01A], an alternate transmit clock source must be  
provided when this loopback is activated. Possible configurations include selecting the TCKI  
pin or CLADO as the transmit clock source, or programming the JAT in the transmit direction  
and setting JFREE to enable the free-running 10 MHz reference [JAT_CR register; addr 002].  
0 = no loopback  
1 = analog loopback  
015External Data Link Time Slot (DL3_TS)  
DL3_TS works in conjunction with the DL3_BIT register [addr 016] to determine which transmit time slots are  
supplied from the TDLI pin, and which receive and transmit time slots are accompanied by a gated RDLCKO  
and TDLCKO output. (Refer to Figure 2-29, Transmit External Data Link Waveforms, Transmit External Data  
Link Waveforms). RDLO outputs the entire receive data bit stream, and only selective digits are marked by  
RDLCKO.  
7
6
5
4
3
2
1
0
DL3EN  
FS[1]  
FS[0]  
TS[4]  
TS[3]  
TS[2]  
TS[1]  
TS[0]  
DL3EN  
Enable External Data LinkActive-high enables data insertion from TDLI and enables clock  
gating on TDLCKO and RDLCKO outputs according to the selected external data link mode.  
NOTE:  
PIO [addr 018] must select TDL_IO and/or RDL_IO to enable external data link  
signals. Bits 5 and 6 must be written to 1s for the External Data Link to operate  
correctly.  
0 = external data link pins inactive  
1 = TDLI/TDLCKO and RDLO/RDLCKO active  
FS[1:0]  
External Data Link Frame SelectThe External data link can be programmed to source and  
sink data bits during all frames, odd frames, or even frames. FS[1:0] controls gating of  
RDLCKO and TDLCKO external data link clocks.  
FS[1:0]  
00  
Frame Select (T1 Mode)  
None. Equivalent to disabling external data link.  
Odd frames only: Frames 1, 3, 5, etc.  
Even frames only: Frames 2, 4, 6, etc.  
All frames.  
01  
10  
11  
FS[1:0]  
00  
Frame Select (E1 Mode)  
None. Equivalent to disabling external data link.  
Even frames only: Frames 0, 2, 4, 6, etc.  
Odd frames only: Frames 1, 3, 5, etc.  
All frames.  
01  
10  
11  
3-28  
Conexant  
N8370DSE  
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