3.0 Registers
Bt8370/8375/8376
3.6 Primary Control and Status Registers
Fully Integrated T1/E1 Framer and Line Interface
01A—Clock Input Mux (CMUX)
7
6
5
4
3
2
1
0
RSBCKI[1]
RSBCKI[0]
TSBCKI[1]
TSBCKI[0]
CLADI[1]
CLADI[0]
TCKI[1]
TCKI[0]
RSBCKI[1:0]
RSBCKI Source Select—The internal clock mux selects 1 of four clock signals for application
to the RSB timebase. RSBCKI input pin is ignored when a clock source other than RSBCKI is
selected.
RSBCKI[1:0]
RSBCKI
Source
Notes
00
01
10
11
RSBCKI
TSBCKI
CLADI
Pin
Pin
Pin
Normal RSB timebase
RSB slaved to TSB
RSB slaved to CLAD input pin
CLADO
Internal CLAD (before output
buffer).
TSBCKI[1:0]
TSBCKI Source Select—The internal clock mux selects 1 of four clock signals for application
to the TSB timebase. TSBCKI input pin is ignored when a clock source other than TSBCKI is
selected. If TSLIP is bypassed [TSB_CR; addr 0D4], TSBCKI is not used, and the transmit
data on TPCMI must be aligned with the TCKI source selected below.
TSBCKI[1:0]
TSBCKI
Source
Notes
00
01
10
11
TSBCKI
RSBCKI
CLADI
Pin
Pin
Pin
Normal TSB timebase
TSB slaved to RSB
TSB slaved to CLAD input
CLADO
Internal CLAD (before output
buffer).
XX
none
When TSLIP is bypassed
CLADI[1:0]
CLADI Source Select—The internal clock mux selects 1 of four clock signals. The selected
clock signal acts as a CLAD input timing reference when the CLAD is enabled [CEN; addr
090]. CLADI input pin is ignored whenever a clock source other than CLADI is selected.
CLADI[1:0]
CLADI
Source
Notes
00
01
CLADI
RCKO
Pin
Normal CLAD input timing
Internal RCKO (before output
buffer).
10
11
TSBCKI
TCKI
Pin
Pin
CLAD slaved to TSB
CLAD slaved to transmit
3-36
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
