2.0 Circuit Description
Bt8370/8375/8376
2.12 Joint Test Access Group
Fully Integrated T1/E1 Framer and Line Interface
2.12 Joint Test Access Group
The Bt8370/8375/8376 incorporates printed circuit board testability circuits in
compliance with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and
Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action
Group).
The JTAG includes a Test Access Port (TAP) and several data registers. The
TAP provides a standard interface through which instructions and test data are
communicated (see Figure 2-49). A Boundary Scan Description Language
(BSDL) file for the Bt8370/8375/8376 is available from the factory upon request.
The test access port consists of the TDI, TCK, TMS, and TDO pins. An
internal power on reset circuit resets the JTAG port.
Figure 2-49. JTAG Diagram
TCK
TMS
JTAG Port
TDI
TDO
2.12.1 Instructions
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST
instructions, IDCODE instruction is supported. There are also two private
instructions. Table 2-25 lists the JTAG instructions, and their codes.
Table 2-25. JTAG Instructions
Instruction
Code
BYPASS
SAMPLE/PRELOAD
EXTEST
111 111
000 001
000 000
000 010
xxx xxx
xxx xxx
IDCODE
Private
Private
2-88
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
