CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.8 FEAC Channel and HDLC Data Link Programming
2.8.4.1 Receiver
Operation
The receiver implements an HDLC data link per ITU standard Q.921. The
functions provided by the data link receiver circuitry are transparency-zero
removal, FCS checking, idle flag reception, and abort flag reception. There are no
restrictions on the total length of the message. Q.921 requires that all messages be
an integral number of 8-bit bytes. If the receiver receives a message that is not an
integral number of bytes, the receiver status indicates a message received with
bad FCS. The per-byte reception times are equivalent to those given for the
transmitter for any particular mode.
The receiver powers up in an indeterminate state. It is initialized by the receipt
of an idle flag (0x7E) on the link, which sets Idle Code Received = 1 in the data
link status register (bits 13-8 of 0x60). When the idle flag is removed from the
link and a message starts coming in, the receiver removes stuffed 0s and writes
the resulting data to the receive data link buffer beginning with the least
significant byte of 0x58 and counting up to the most significant byte of 0x5B.
When the first four bytes have been written, the processor is interrupted to
read the data out of the buffer. The processor has 4 byte intervals to read the data
before it is overwritten with new data. The interrupt is cleared when the processor
reads DL_CTRL_STAT. The status register indicates a message in progress at this
time:
•
•
Idle Code Received = 0
RxBytes[2:0] = 3
If the upper half of the buffer had just been filled, the status register indicates
RxBytes[2:0] = 7, and locations 4 through 7 must be read during the next 4 byte
intervals to retrieve the message.
When the last block of data has been received, the processor is again
interrupted. This time, the data link status register indicates the end of message:
•
•
•
Idle Code Received = 1
RxBytes[2:0] = n
Bad FCS = 0 or 1
The RxBytes[2:0] = n portion of the register indicates the highest-numbered
location that was written in the receive buffer. Locations 0 to n or 4 to m (where
n = 0 to 3 and m = 4 to 7) must be read to retrieve the data depending on what has
already been read at the previous interrupt. The two highest-numbered locations
contain the FCS that was received at the end of the message. A new incoming
message always starts in the opposite buffer half from where the previous
message ended to prevent overwriting of previously received bytes and allow the
processor time to retrieve those bytes. For example, if a message ended in buffer
0x5A or 0x5B, the next message received would be stored starting in 0x58. If a
message ended in buffer 0x58 or 0x59, the next message received would be stored
starting in 0x5A.
If the received message is a multiple of 8 bytes, then when the processor is
interrupted to read the last block of data, the FCS has yet to be received. In this
event, the processor is again interrupted when the FCS has been checked, and an
idle flag received. The data link status register shows RxBytes[2:0] = 1 (or 5),
FCS good or bad, and Idle Code Received = 1; and the FCS that was received will
be in locations 0 and 1 (or 4 and 5). Again, the data must be read out during the
next 4 byte intervals, or it may be overwritten by a new incoming message.
100046C
Conexant
2-49
CONEXANT [ CONEXANT SYSTEMS, INC ]
