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MX909ADW 参数 Datasheet PDF下载

MX909ADW图片预览
型号: MX909ADW
PDF下载: 下载PDF文件 查看货源
内容描述: GMSK调制解调器数据泵 [GMSK Modem Data Pump]
分类和应用: 调制解调器
文件页数/大小: 38 页 / 359 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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GMSK Modem Data Pump  
Page 18 of 37  
MX909A PRELIMINARY INFORMATION  
4.4.3.2 Control Register B4: DARA - Data Rate  
This bit operates in both transmit and receive modes, optimizing the modem's internal signal filtering  
according to the relevant bit rate.  
If the bit rate used is above 10k bits/sec then this bit should be set to '1' , if not, then it should be set to '0'.  
4.4.3.3 Control Register B3, B2: LEVRES - Level Measurement Response Time  
These two bits have no effect in transmit mode.  
In receive mode, they set the 'normal' response time of the Rx signal amplitude and DC offset measuring  
circuits. This setting will be temporarily overridden by the automatic sequencing of an AQLEV command.  
B3 B2  
0
0
1
1
0
1
0
1
Hold  
Keep current values of amplitude and offset  
Track input signal using bit peak averaging  
Track input signal using peak detect  
Peak Averaging  
Peak Detect  
Lossy Peak Detect Track input signal using lossy peak detection  
For Mobitex¥ systems, and most general purpose applications using the modem, these bits should normally  
be set to 'Peak Averaging', except when the µC detects a receive signal fade, when 'Hold' should be selected.  
The 'Lossy Peak Detect' setting is intended for systems where the µC cannot detect signal fades or the start  
of a received message, as it allows the modem to respond quickly to fresh messages and recover rapidly  
after a fade without µC intervention - although at the cost of reduced Bit Error Rate versus Signal to Noise  
performance.  
Note: Since the measured levels are stored on the external capacitors C6 and C7, they will decay gradually  
towards V  
when the 'Hold' setting is chosen, the discharge time-constant being approximately 2000  
BIAS  
bit times. Further information of the level measurement system is provided in section 5.3.  
4.4.3.4 Control Register B1, B0: PLLBW  
These two bits have no effect in transmit mode.  
In receive mode, they set the 'normal' bandwidth of the Rx clock extraction Phase Locked Loop circuit. This  
setting will be temporarily overridden by the automatic sequencing of an AQBC command.  
B1 B0 PLL Bandwidth  
Suggested use  
0
0
1
1
0
1
0
1
Hold  
Signal fades  
Narrow  
Medium  
Wide  
± 20ppm or better Xtals  
Wide tolerance Xtals or long preamble acquisition  
Quick acquisition  
The 'hold' setting is intended for use during signal fades, otherwise the minimum bandwidth consistent with  
the transmit and receive modem bit rate tolerances should be chosen.  
The wide and medium bandwidth settings are intended for systems where the µC cannot detect signal fades  
or the start of a received message, as they allow the modem to respond rapidly to fresh messages and  
recover rapidly after a fade without µC intervention - although at the cost of reduced Bit Error Rate versus  
Signal to Noise performance.  
Note: Further information of the clock extraction system is provided in section 5.3.  
¤2001 MX-COM, Inc.  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054  
Doc. # 20480134.005  
All trademarks and service marks are held by their respective companies.  
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