GMSK Modem Data Pump
Page 14 of 37
MX909A PRELIMINARY INFORMATION
4.4.2.6 SFH - Search for Frame Head
Causes the modem to search the received signal for a Frame Head. The Frame Head will consist of a 16-bit
Frame Sync followed by control data (see Figure 6). The search will continue until a Frame Head has been
found, or until the RESET task is loaded.
The search is carried out by first attempting to match the incoming bits against the previously programmed
(task LFSB) 16-bit Frame Sync pattern (allowing up to any one bit (of 16) in error). When a match has been
found, the modem will read the next 3 received bytes as Frame Head bytes, these bytes will be checked, and
corrected if necessary, using the FEC bits. The two Frame Head Data bytes are then placed into the Data
Buffer.
The BFREE and IRQ bits of the Status Register will then be set to a logic '1' to indicate that the µC may read
the 2 Frame Head Data bytes from the Data Buffer and write the next task to the Command Register. If the
FEC indicates uncorrectable errors the modem will set the CRCFEC bit in the Status Register to a logic '1'.
The MO/BA bit (Mobile or Base) in the Status Register will be set according to the polarity of the 3 bits
preceding the Frame Sync pattern.
4.4.2.7 R3H - Read 3-byte Frame Head
This task, which would normally follow an SFS task, will place the next 3 bytes directly into the Data Buffer. It
also causes the modem to check the 3 bytes as Frame Head control data bytes and will set the CRCFEC bit
to a logic '1' only if the FEC bits indicate uncorrectable errors.
Note: This task will not correct any errors and, due to the Mobitex¥ FEC specification, will not detect all
possible uncorrectable error patterns. The BFREE and IRQ bits of the Status Register will be set to '1'
when the task is complete to indicate that the µC may read the data from the Data Buffer and write the
next task to the modem's Command Register.
The CRCFEC bit in the Status Register will be set according to the validity of the received FEC bits.
4.4.2.8 RDB - Read Data Block
This task causes the modem to read the next 240 bits as a Mobitex¥ Data Block.
It will de-scramble and de-interleave the bits, FEC correct and CRC check the resulting 18 data bytes and
place them into the Data Buffer, setting the BFREE and IRQ bits of the Status Register to '1' when the task is
complete to indicate that the µC may read the data from the Data Buffer and write the next task to the
modem's Command Register. The CRCFEC bit will be set according to the outcome of the CRC check.
Note: In receive mode the CRC checksum circuits are initialized on completion of any task other than NULL.
4.4.2.9 SFS - Search for Frame Sync
This task, which is intended for special test and channel monitoring purposes, performs the first part only of a
SFH task. It causes the modem to search the received signal for a 16-bit sequence which matches the
Frame Synchronization pattern with up to any 1 bit in error.
When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' and update
the MO/BA bit. The µC may then write the next task to the Command Register.
4.4.2.10 RSB - Read Single Byte
This task causes the modem to read the next 8 bits and translate them directly (without de-interleaving or
FEC) to an 8-bit byte which is placed into the Data Buffer (B7 will represent the earliest bit received). The
BFREE and IRQ bits of the Status Register will then be set to '1' to indicate that the µC may read the data
byte from the Data Buffer and write the next task to the Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by an SFS task.
4.4.2.11 LFSB - Load Frame Sync Bytes
This task takes 2 bytes from the Data Buffer and updates the Frame Sync detect bytes. The MSB of byte '0'
is compared to the first bit of a received Frame Sync pattern and the LSB of byte '1' is compared to the last bit
of a received Frame Sync pattern. This task does not enable Frame Sync detection.
Unlike other Rx tasks, the data buffer must be loaded before the task is issued and the task must only be
issued 'between' received messages, i.e. before the first task for receiving a message and after the last data
is read out of the data buffer.
Once the modem has read the Frame Sync bytes from the Data Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1', indicating to the µC that it may write the next task to the modem.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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