GMSK Modem Data Pump
Page 19 of 37
MX909A PRELIMINARY INFORMATION
4.4.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register
7 6 5 4 3 2 1 0
Tx/Rx
IRQEN INVBIT
SCREN PSAVE DQEN
Reserved
set to '0 0'
4.4.4.1 Mode Register B7: IRQEN- IRQ Output Enable
When this bit is set to '1', the IRQ chip output pin is pulled low (to V ) whenever the IRQ bit of the Status
SS
Register is a '1'.
4.4.4.2 Mode Register B6: INVBIT - Invert Bits
This bit controls inversion of transmitted and received bit voltages. When set to '1' all data is inverted in the
Tx and Rx data paths so a transmitted '1' is a voltage below V
at the TXOUT pin and a received '0' is a
BIAS
voltage above V
at the RXIN pin. Data will be inverted immediately after this bit is set to '1'.
BIAS
4.4.4.3 Mode Register B5: TX/RX - Tx/Rx Mode
Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode.
When changing from Rx to Tx there must be a 2-bit pause before setting a new task to allow the filter to
stabilize. (See also PSAVE bit).
Note: Changing between receive and transmit modes will cancel any current task
4.4.4.4 Mode Register B4: SCREN - Scramble Enable
The scrambler only takes effect during the transmission or reception of a Mobitex¥ Data Block and during a
TSO task. Setting this bit to '1' enables scrambling, clearing it to '0' disables scrambling.
The scrambler is only operative, if enabled by this control bit, during TSO, RDB or TDB, it is held in a reset
state at all other times.
This bit should not be changed while the modem is decoding or transmitting a Mobitex¥ Data Block.
4.4.4.5 Mode Register B3: PSAVE - Powersave
When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx bit and
Clock extraction circuits and the Tx output buffer will be disabled, and the TXOUT pin will be connected to
V
BIAS
through a high value resistance. The Xtal Clock oscillator and the µC interface logic will continue to
operate.
Setting the PSAVE bit to '0' restores power to all of the chip circuitry.
Note: The internal filters will take approximately 2 bit times to settle after the PSAVE bit is taken from '1' to '0'.
4.4.4.6 Mode Register B2: DQEN - Data Quality IRQ Enable
In receive mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a new
Data Quality reading is ready. (The DQRDY bit of the Status Register will also be set to '1' at the same time.)
In transmit mode this bit has no effect.
4.4.4.7 Mode Register B1, B0
These bits should be set to '0'.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
All trademarks and service marks are held by their respective companies.
CMLMICRO [ CML MICROCIRCUITS ]
